Abstract: A method for controlling a data processing system includes detecting a droop in a power supply voltage of a functional circuit of the data processing system greater than a programmable droop threshold. An operation of the data processing system is throttled according to a programmable step size, a programmable assertion time, and a programmable de-assertion time in response to detecting the droop.

Abstract: A multiply-accumulate computation is performed using digital logic circuits. To perform the computation, a plurality of target signals are received at a respective plurality of ripple counters. The counter outputs of the respective ripple counters are scaled by setting stop count values. Counter outputs of the respective ripple counters are adjusted with respective constant values by setting counter reset values at the respective ripple counters. Each count pulses of the target signals for an adjusted period. The count values of the ripple counters are summed. The results may be used to calculate an average value for an adaptive voltage and frequency scaling process.

Abstract: An oscillator circuit is provided that adapts to voltage supply variations. The circuit first and second delays lines connected inputs of an edge detector, one delay line supplied by a reference voltage and the other with a drooping supply voltage. The edge detector generates an output clock based on a relationship between the inputs. The output clock applied to the signal inputs of the first and second delay lines. The output clock has a voltage dependent frequency performance curve with a slope dependent at least on the second delay line delay and a delay of the edge detector. At least one of the first delay line, the second delay line, and the edge detector delay are adjusted to change the slope of the performance curve.

Abstract: A apparatus includes a reference signal generator, a droop detection circuit, a digital frequency-locked loop (DFLL), and a DFLL control circuit. The reference signal generator that receives a digital value and produces a pulse-density modulated signal based on the digital value. The droop detection circuit converts the pulse-density modulated signal to an analog signal, compares the analog signal to a monitored supply voltage, and responsive to detecting a droop of the monitored supply voltage below a designated value relative to the analog signal, produces a droop detection signal. The DFLL provides a clock signal for synchronizing circuitry within a domain of the monitored supply voltage. The DFLL control circuit, responsive to receiving the droop detection signal, causes the DFLL to slow the clock signal.

Abstract: A power supply monitor includes a droop detection circuit which receives a digital signal and converts the digital signal to an analog signal, compares the analog signal to a monitored supply voltage, and responsive to detecting a droop below a designated value relative to the analog signal, produces a droop detection signal. The droop detection circuit includes a first comparator circuit with a series of inverters including at least a first complimentary-metal-oxide-semiconductor (CMOS) inverter with an input for receiving the analog signal and a second CMOS inverter, which are both supplied with a monitored supply voltage. The inverters operate in a crowbar mode when the monitored voltage supply is near a designated level, and each include four pull-up transistors connected in two parallel legs of two transistors, and four pull-down transistors connected in two parallel legs of two transistors.

Abstract: A apparatus includes a reference signal generator, a droop detection circuit, a digital frequency-locked loop (DFLL), and a DFLL control circuit. The reference signal generator that receives a digital value and produces a pulse-density modulated signal based on the digital value. The droop detection circuit converts the pulse-density modulated signal to an analog signal, compares the analog signal to a monitored supply voltage, and responsive to detecting a droop of the monitored supply voltage below a designated value relative to the analog signal, produces a droop detection signal. The DFLL provides a clock signal for synchronizing circuitry within a domain of the monitored supply voltage. The DFLL control circuit, responsive to receiving the droop detection signal, causes the DFLL to slow the clock signal.

Abstract: A method for controlling a data processing system includes detecting a droop in a power supply voltage of a functional circuit of the data processing system greater than a programmable droop threshold. An operation of the data processing system is throttled according to a programmable step size, a programmable assertion time, and a programmable de-assertion time in response to detecting the droop.

Abstract: A power supply monitor includes a delta-sigma modulator including an input receiving a binary number and an output providing a pulse-density modulated signal, the delta-sigma modulator operable to scale the pulse-density modulated signal based on the binary number. A fast droop detector circuit includes a level shifter providing the modulated signal referenced to a clean supply voltage. A lowpass filter is coupled between the level shifter and a comparator. The comparator produces a droop detection signal at said output responsive to a monitored supply voltage dropping below a predetermined level relative to the filtered signal.

Abstract: A power supply monitor includes a delta-sigma modulator including an input receiving a binary number and an output providing a pulse-density modulated signal, the delta-sigma modulator operable to scale the pulse-density modulated signal based on the binary number. A fast droop detector circuit includes a level shifter providing the modulated signal referenced to a clean supply voltage. A lowpass filter is coupled between the level shifter and a comparator. The comparator produces a droop detection signal at said output responsive to a monitored supply voltage dropping below a predetermined level relative to the filtered signal.

Abstract: An integrated circuit includes a plurality of tiles receiving a power supply voltage, each having a corresponding analog circuit and operates in response to a first voltage, and a hardware controller receiving a voltage identification code and provides the first voltage to each of the plurality of tiles in response thereto. The hardware controller comprises a test time controller determining coefficients of a waveform that describes an average correspondence between the power supply voltage and the first voltage for the plurality of tiles, and a boot time controller determining a respective error signal indicating an error between the waveform and a respective actual waveform for each of the plurality of tiles, and providing the respective error signal to the corresponding analog circuit of each of the plurality of tiles. The corresponding analog circuit of each of the plurality of tiles adjusts the first voltage according to the respective error signal.

Abstract: A power regulator provides current to a processing unit. A clock distribution network provides a clock signal to the processing unit. A level-based droop detector monitors a voltage of the current provided to the processing unit and provides a droop detection signal to the clock distribution network in response to the voltage falling below a first threshold voltage. The clock distribution network decreases a frequency of a clock signal provided to the processing unit in response to receiving the droop detection signal. The level-based droop detector interrupts the droop detection signal that is provided to the clock distribution network in response to the voltage rising above a second threshold voltage. The clock distribution network increases the frequency of the clock signal provided to the processing unit in response to interruption of the droop detection signal.

Abstract: An integrated circuit includes a plurality of tiles receiving a power supply voltage, each having a corresponding analog circuit and operates in response to a first voltage, and a hardware controller receiving a voltage identification code and provides the first voltage to each of the plurality of tiles in response thereto. The hardware controller comprises a test time controller determining coefficients of a waveform that describes an average correspondence between the power supply voltage and the first voltage for the plurality of tiles, and a boot time controller determining a respective error signal indicating an error between the waveform and a respective actual waveform for each of the plurality of tiles, and providing the respective error signal to the corresponding analog circuit of each of the plurality of tiles. The corresponding analog circuit of each of the plurality of tiles adjusts the first voltage according to the respective error signal.

Abstract: A data processor includes at least one power supply voltage terminal for receiving a power supply voltage and a power supply current, a data processing circuit, a register, and a port controller. The data processing circuit is coupled to the at least one power supply voltage terminal and operates using the power supply voltage. The register stores a nominal value of the power supply voltage, an electrical design current (EDC) limit, and an EDC slope, wherein the EDC slope specifies a desired voltage-current relationship for an external voltage regulator when the power supply current exceeds the EDC limit. The port controller is coupled to the register and to an output port. The data processing circuit is operative to cause the port controller to output the nominal value of the power supply voltage, the EDC limit, and the EDC slope over the output port for use by the external voltage regulator.

Abstract: A processor adjusts the voltage margin of a supply voltage based on a sampled clock frequency. The processor generates the supply voltage by combining the voltage margin with a specified nominal voltage, and provides the supply voltage to a processor module, such as graphics processing unit (GPU). In addition, an adaptive clock module (e.g., a digital frequency-locked loop) generates a clock signal for the processor module, wherein the frequency of the clock signal varies at least in part based on the supply voltage. The processor samples the frequency of the clock signal and adjusts the voltage margin based on the sampled frequency. The processor thereby keeps excursions in the clock frequency within a specified limit, thus supporting a relatively stable clock frequency.

Abstract: A multiply-accumulate computation is performed using digital logic circuits. To perform the computation, a plurality of target signals are received at a respective plurality of ripple counters. The counter outputs of the respective ripple counters are scaled by setting stop count values. Counter outputs of the respective ripple counters are adjusted with respective constant values by setting counter reset values at the respective ripple counters. Each count pulses of the target signals for an adjusted period. The count values of the ripple counters are summed. The results may be used to calculate an average value for an adaptive voltage and frequency scaling process.

Abstract: Systems, apparatuses, and methods for dynamically generating a memory bitcell supply voltage rail from a logic supply voltage rail are disclosed. A circuit includes at least one or more comparators, control logic, and power stage circuitry. The circuit receives a logic supply voltage rail and compares the logic supply voltage rail to threshold voltage(s) using the comparator(s). Comparison signal(s) from the comparator(s) are coupled to the control logic. The control logic generates mode control signals based on the comparison signal(s) and based on a programmable dynamic range that is desired for a memory bitcell supply voltage rail. The mode control signals are provided to the power stage circuitry which generates the memory bitcell supply voltage rail from the logic supply voltage rail. A voltage level of the memory bitcell supply voltage rail can be above, below, or the same as the logic supply voltage rail.

Abstract: In one form, a power supply monitor including a current controlled oscillator circuit, a time-to-digital converter, and an output divider. The current controlled oscillator circuit has an input for receiving a power supply voltage to be measured, and an output for providing a frequency signal having a frequency linearly proportional to the power supply voltage. The time-to-digital converter has an input coupled to the output of the current controlled oscillator circuit, and an output for providing a count signal representative of a number of cycles of a reference clock signal per cycle of the frequency signal. The output divider has an input coupled to the output of the time-to-digital converter, and an output for providing a divided count signal representative of a value of the power supply voltage, and provides the divided count signal by dividing a fixed number by the count signal.

Abstract: A data processor includes at least one power supply voltage terminal for receiving a power supply voltage and a power supply current, a data processing circuit, a register, and a port controller. The data processing circuit is coupled to the at least one power supply voltage terminal and operates using the power supply voltage. The register stores a nominal value of the power supply voltage, an electrical design current (EDC) limit, and an EDC slope, wherein the EDC slope specifies a desired voltage-current relationship for an external voltage regulator when the power supply current exceeds the EDC limit. The port controller is coupled to the register and to an output port. The data processing circuit is operative to cause the port controller to output the nominal value of the power supply voltage, the EDC limit, and the EDC slope over the output port for use by the external voltage regulator.

Abstract: An oscillator circuit includes a first oscillator, a second oscillator, and a calibration circuit to calibrate the first and second oscillators. The first oscillator is supplied with a first supply voltage, and the second oscillator is supplied with a second supply voltage. The calibration includes setting a frequency control of the second oscillator at a target frequency. Then, a voltage control of the second supply voltage is adjusted incrementally until a first control value is identified at which a second oscillator output frequency matches the target frequency. Then, a voltage control of the first supply voltage is set to the first control value. Then, the voltage control for the first supply voltage is adjusted incrementally until a second control value is identified at which a first oscillator output frequency is as close to the second oscillator output frequency as is achievable, but does not exceed it.

Abstract: Systems, apparatuses, and methods for dynamically generating a memory bitcell supply voltage rail from a logic supply voltage rail are disclosed. A circuit includes at least one or more comparators, control logic, and power stage circuitry. The circuit receives a logic supply voltage rail and compares the logic supply voltage rail to threshold voltage(s) using the comparator(s). Comparison signal(s) from the comparator(s) are coupled to the control logic. The control logic generates mode control signals based on the comparison signal(s) and based on a programmable dynamic range that is desired for a memory bitcell supply voltage rail. The mode control signals are provided to the power stage circuitry which generates the memory bitcell supply voltage rail from the logic supply voltage rail. A voltage level of the memory bitcell supply voltage rail can be above, below, or the same as the logic supply voltage rail.