Patents by Inventor Stephen W. Melvin

Stephen W. Melvin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8732482
    Abstract: A method and apparatus are utilized to incrementally encrypt stored information, and can be applied to an existing medium storing unencrypted information. Information can be conditionally encrypted and/or decrypted as necessary and a separate storage area can be used to record whether a given block of information is stored encrypted or unencrypted. An embodiment of the present invention can be used as a retrofit device in a mechanism to encrypt information without causing undue interruption of normal operations. A variety of mechanisms and policies can also be used to manage, set and eliminate encryption keys.
    Type: Grant
    Filed: September 24, 2012
    Date of Patent: May 20, 2014
    Inventor: Stephen W. Melvin
  • Publication number: 20100202292
    Abstract: A processing engine to accomplish a multiplicity of tasks has a multiplicity of processing tribes, each tribe comprising a multiplicity of context register sets and a multiplicity of processing resources for concurrent processing of a multiplicity of threads to accomplish the tasks, a memory structure having a multiplicity of memory blocks, each block storing data for processing threads, and an interconnect structure and control system enabling tribe-to-tribe migration of contexts to move threads from tribe-to-tribe. The processing engine is characterized in that individual ones of the tribes have preferential access to individual ones of the multiplicity of memory blocks.
    Type: Application
    Filed: January 29, 2010
    Publication date: August 12, 2010
    Inventors: Mario D. Nemirovsky, Enrique Musoll, Jeffrey T. Huynh, Stephen W. Melvin
  • Patent number: 7360217
    Abstract: A processing engine to accomplish a multiplicity of tasks has a multiplicity of processing tribes, each tribe comprising a multiplicity of context register sets and a multiplicity of processing resources for concurrent processing of a multiplicity of threads to accomplish the tasks, a memory structure having a multiplicity of memory blocks, each block storing data for processing threads, and an interconnect structure and control system enabling tribe-to-tribe migration of contexts to move threads from tribe-to-tribe. The processing engine is characterized in that individual ones of the tribes have preferential access to individual ones of the multiplicity of memory blocks.
    Type: Grant
    Filed: September 24, 2002
    Date of Patent: April 15, 2008
    Assignee: ConSentry Networks, Inc.
    Inventors: Stephen W. Melvin, Mario D. Nemirovsky, Enrique Musoll, Jeffery T. Huynh
  • Patent number: 7035998
    Abstract: A pipelined multistreaming processor has an instruction source, a first cluster of a plurality of streams fetching instructions from the instruction source, a second cluster of a plurality of streams fetching instructions from the instruction source, dedicated instruction queues for individual streams in each cluster, a first dedicated dispatch stage in the first cluster for dispatching instructions to execution units, and a second dedicated dispatch stage in the second cluster for selecting and dispatching instructions to execution units. The processor is characterized in that the clusters operate independently, with the dedicated dispatch stage taking instructions only from the instruction queues in the individual clusters to which the dispatch stages are dedicated. In preferred embodiments there are dedicated fetch and dispatch stages for streams in the clusters, and dedicated execution units to which instructions may be dispatched.
    Type: Grant
    Filed: November 3, 2000
    Date of Patent: April 25, 2006
    Assignee: MIPS Technologies, Inc.
    Inventors: Mario Nemirovsky, Stephen W. Melvin, Nandakumar Sampath, Enrique Musoll, Hector Urdaneta
  • Publication number: 20030069920
    Abstract: A processing engine to accomplish a multiplicity of tasks has a multiplicity of processing tribes, each tribe comprising a multiplicity of context register sets and a multiplicity of processing resources for concurrent processing of a multiplicity of threads to accomplish the tasks, a memory structure having a multiplicity of memory blocks, each block storing data for processing threads, and an interconnect structure and control system enabling tribe-to-tribe migration of contexts to move threads from tribe-to-tribe. The processing engine is characterized in that individual ones of the tribes have preferential access to individual ones of the multiplicity of memory blocks.
    Type: Application
    Filed: September 24, 2002
    Publication date: April 10, 2003
    Inventors: Stephen W. Melvin, Mario D. Nemirovsky, Enrique Musoll, Jeffery T. Huynh