Patents by Inventor Stephen W. SOMOGYI

Stephen W. SOMOGYI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Selective generation of miss requests for cache lines
    Patent number: 11720499
    Abstract: A graphics pipeline includes a texture cache having cache lines that are partitioned into a plurality of subsets. The graphics pipeline also includes one or more compute units that selectively generates a miss request for a first subset of the plurality of subsets of a cache line in the texture cache in response to a cache miss for a memory access request to an address associated with the first subset of the cache line. In some embodiments, the cache lines are partitioned into a first sector and a second sector. The compute units generate miss requests for the first sector, and bypass generating miss requests for the second sector, in response to cache misses for memory access requests received during a request cycle being in the first sector.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: August 8, 2023
    Assignees: Advanced Micro Devices, Inc., SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Fataneh Ghodrat, Stephen W. Somogyi, Zhenhong Liu
  • SELECTIVE GENERATION OF MISS REQUESTS FOR CACHE LINES
    Publication number: 20220206950
    Abstract: A graphics pipeline includes a texture cache having cache lines that are partitioned into a plurality of subsets. The graphics pipeline also includes one or more compute units that selectively generates a miss request for a first subset of the plurality of subsets of a cache line in the texture cache in response to a cache miss for a memory access request to an address associated with the first subset of the cache line. In some embodiments, the cache lines are partitioned into a first sector and a second sector. The compute units generate miss requests for the first sector, and bypass generating miss requests for the second sector, in response to cache misses for memory access requests received during a request cycle being in the first sector.
    Type: Application
    Filed: December 28, 2020
    Publication date: June 30, 2022
    Inventors: Fataneh GHODRAT, Stephen W. SOMOGYI, Zhenhong LIU