Abstract: A computer system supports control transfers between two architectures with different address ranges and/or different methods of calling programs which involve passing parameters, stack pointers and return addresses. Control is transferred between the architectures through a control transfer mode bit.

Abstract: An apparatus for use with a computer system for identifying dependencies within a register, which dependencies are established by a succession of instructions for the computer system. The register includes a plurality of cells which may be in a hierarchical arrangement of register storage sets. In its preferred embodiment, the apparatus comprises a storage means for storing a bit map, which bit map is configured to provide bit map identifications identifying designated register storage sets. The bit map represents the hierarchical arrangement. The apparatus further comprises a logic means for logically treating information, which logic means is coupled with the storage means and with the computer system. The logic means receives a first bit map identification from a first instruction (the first bit map identification identifies a first register storage set), and receives a second bit map identification from a second instruction (the second bit map identification identifies a second register storage set.

Abstract: A computer processor architecture which employs an on-chip cache macro and an on-chip memory map is described. The memory map contains indicia of the cachability of different segments of off-chip memory, preferably along with an indication of the read/write status of each off-chip memory segment. A processor generated address signal is then compared on-chip with the memory map to ascertain whether the generated signal falls within a segment which is cachable or uncachable and which is read-only or read/write.

Abstract: A mechanism which manages variable length instructions in cache is comprised of three cooperating elements designed to optimize self modifying code and anticipate next instructions for branch operand management. A content addressable memory (CAM) stores addresses of lines which have been accessed for instruction fetching. In a system having modifiable instruction stream (i.e., store to instruction stream), when the CAM matches, the system must retire certain instructions, flush instructions and then fetch the modified instruction stream. Boundary identification logic examines a field in each cache byte to determine the nature of the byte. This field is initially cleared at the time the cache line is loaded and filled with the line is fetched. An anticipation buffer designed to minimize the circuitry necessary for fetches across cache lines is loaded with sequentially anticipated prefetched instructions from the cache. These anticipated instructions can then be concatenated by a fetch aligner.

Abstract: A mechanism which manages variable length instructions in cache is comprised of three cooperating elements designed to optimize self modifying code and anticipate next instructions for branch operand management. A content addressable memory (CAM) stores addresses of lines which have been accessed for instruction fetching. In a system having modifiable instruction stream (i.e., store to instruction stream), when the CAM matches, the system must retire certain instructions, flush instructions and then fetch the modified instruction stream. Boundary identification logic examines a field in each cache byte to determine the nature of the byte. This field is initially cleared at the time the cache line is loaded and filled with the line is fetched. An anticipation buffer designed to minimize the circuitry necessary for fetches across cache lines is loaded with sequentially anticipated prefetched instructions from the cache. These anticipated instructions can then be concatenated by a fetch aligner.