Patents by Inventor Stevan G. Hunter

Stevan G. Hunter has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9189585
    Abstract: A design rule checker that performs a maximum pattern density check in a first intermediary metallization layer that underlies a top metallization layer and a pad opening in an integrated circuit. The maximum pattern density check is performed at least under some circumstances if a modulus of the primary metallization material is less than a modulus of a surrounding dielectric material. The maximum pattern density check verifies that the pattern density within the underlying portion is below a maximum pattern density that depends on the thickness of the access pad. A maximum metal width check may also be performed in this portion.
    Type: Grant
    Filed: June 27, 2014
    Date of Patent: November 17, 2015
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC.
    Inventors: Stevan G. Hunter, Bryce A. Rasmussen, Troy L. Ruud
  • Publication number: 20140310669
    Abstract: A design rule checker that performs a maximum pattern density check in a first intermediary metallization layer that underlies a top metallization layer and a pad opening in an integrated circuit. The maximum pattern density check is performed at least under some circumstances if a modulus of the primary metallization material is less than a modulus of a surrounding dielectric material. The maximum pattern density check verifies that the pattern density within the underlying portion is below a maximum pattern density that depends on the thickness of the access pad. A maximum metal width check may also be performed in this portion.
    Type: Application
    Filed: June 27, 2014
    Publication date: October 16, 2014
    Inventors: Stevan G. Hunter, Bryce A. Rasmussen, Troy L. Ruud
  • Publication number: 20130154099
    Abstract: A design rule checker that performs a maximum pattern density check in a first intermediary metallization layer that underlies a top metallization layer and a pad opening in an integrated circuit. The maximum pattern density check is performed at least under some circumstances if a modulus of the primary metallization material is less than a modulus of a surrounding dielectric material. The maximum pattern density check verifies that the pattern density within the underlying portion is below a maximum pattern density that depends on the thickness of the access pad. A maximum metal width check may also be performed in this portion.
    Type: Application
    Filed: December 16, 2011
    Publication date: June 20, 2013
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Stevan G. Hunter, Bryce A. Rasmussen, Troy L. Ruud
  • Publication number: 20040023416
    Abstract: A method is provided for forming a paraelectric semiconductor device by depositing a seed layer on an oxide electrode using a paraelectric material precursor and depositing a paraelectric layer on the seed layer using the paraelectric material precursor.
    Type: Application
    Filed: August 5, 2002
    Publication date: February 5, 2004
    Inventors: Stephen R. Gilbert, Sanjeev Aggarwal, Scott Summerfelt, Stevan G. Hunter
  • Patent number: 6576482
    Abstract: One aspect of the invention relates to a one-step process for forming a transition metal aluminum oxynitride layer over a transition metal aluminum nitride layer. The transition metal aluminum nitride layer is sputter deposited using a transition metal/aluminum target in an atmosphere containing nitrogen. Subsequently, the oxygen content of the atmosphere is increased, whereby the transition metal aluminum oxynitride layer can be deposited without interrupting the process or otherwise reconditioning the target. Another aspect of the invention relates to depositing a transition metal aluminum nitride layer over a transition metal aluminum oxynitride layer by reducing the oxygen content of the atmosphere. The invention provides a one-step process for depositing a hard mask layer and upper diffusion barrier layer for the capacitor stack of a FeRAM. A top electrode, such as an Ir/IrO electrode, can be deposited as part of the one-step process.
    Type: Grant
    Filed: May 7, 2002
    Date of Patent: June 10, 2003
    Assignees: Texas Instruments Incorporated, Agilent Technologies
    Inventors: Sanjeev Aggarwal, Scott R. Summerfelt, Stevan G. Hunter