Abstract: Disclosed is a thermal environment enclosure for a semiconductor test system, said enclosure comprising a housing having an exterior surface, an interior chamber and a window therethrough. The housing further comprised of a substantially rectangular top, a pair of substantially rectangular side walls, a front wall, a back wall, a top perimeter edge, and a bottom perimeter edge with an attached sealing gasket. The bottom perimeter edge defines an opening into the interior chamber which is configured for sealed mating with the recessed test area to define a imposed thermal environment test area. The top of the housing comprises a hingeably attached lid with a closing latch, the lid including an attached interior surface sealing gasket defining the interior chamber in combination with other walls when the lid is closed.

Abstract: A universal testing device for testing a plurality of electronic modules having different configurations and operating parameters. In one embodiment of the invention, a universal mounting board for testing a plurality of different modules with different pin configurations and operating parameters is a printed circuit board with a plurality of connectors and a plurality of conductive contact sites. The connectors of the universal mounting board are arranged to be operatively coupled with a plurality of contacts of a separate control fixture. In general, the contacts of the control fixture are operatively coupled to a supply voltage, a ground plane, and a signal controller. The control fixture also has a sufficient number of contacts to provide the necessary number of inputs/outputs of supply voltage, ground connections, and signals for virtually any type of electronic module.