Patents by Inventor Steve C. Miller

Steve C. Miller has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140365596
    Abstract: A network storage controller uses a non-volatile solid-state memory (NVSSM) subsystem which includes raw flash memory as stable storage for data, and uses remote direct memory access (RDMA) to access the NVSSM subsystem, including to access the flash memory. Storage of data in the NVSSM subsystem is controlled by an external storage operating system in the storage controller. The storage operating system uses scatter-gather lists to specify the RDMA read and write operations. Multiple client-initiated reads or writes can be combined in the storage controller into a single RDMA read or write, respectively, which can then be decomposed and executed as multiple reads or writes, respectively, in the NVSSM subsystem. Memory accesses generated by a single RDMA read or write may be directed to different memory devices in the NVSSM subsystem, which may include different forms of non-volatile solid-state memory.
    Type: Application
    Filed: June 12, 2014
    Publication date: December 11, 2014
    Inventors: Arkady Kanevsky, Steve C. Miller
  • Patent number: 8775718
    Abstract: A network storage controller uses a non-volatile solid-state memory (NVSSM) subsystem which includes raw flash memory as stable storage for data, and uses remote direct memory access (RDMA) to access the NVSSM subsystem, including to access the flash memory. Storage of data in the NVSSM subsystem is controlled by an external storage operating system in the storage controller. The storage operating system uses scatter-gather lists to specify the RDMA read and write operations. Multiple client-initiated reads or writes can be combined in the storage controller into a single RDMA read or write, respectively, which can then be decomposed and executed as multiple reads or writes, respectively, in the NVSSM subsystem. Memory accesses generated by a single RDMA read or write may be directed to different memory devices in the NVSSM subsystem, which may include different forms of non-volatile solid-state memory.
    Type: Grant
    Filed: July 1, 2008
    Date of Patent: July 8, 2014
    Assignee: NetApp, Inc.
    Inventors: Arkady Kanevsky, Steve C. Miller
  • Patent number: 8621142
    Abstract: A technique for achieving consistent read latency from an array of non-volatile solid-state memories involves an external entity determining the “busy” or “not busy” status of non-volatile solid-state memory elements in a RAID group. An external data layout engine then uses parity based RAID data reconstruction to avoid having to read from any memory element that is busy in a RAID group, along with careful scheduling of writes and erasures.
    Type: Grant
    Filed: April 18, 2011
    Date of Patent: December 31, 2013
    Assignee: NetApp, Inc.
    Inventors: Steve C. Miller, Jeffrey S. Kimmel
  • Patent number: 8621146
    Abstract: A network storage system includes “raw” flash memory, and storage of data in that flash memory is controlled by an external, log structured, write out-of-place data layout engine of a storage server. By avoiding a separate, onboard data layout engine on the flash devices, the latency associated with operation of such a data layout engine is also avoided. The flash memory can be used as the main persistent storage of a storage server and/or as buffer cache of a storage server, or both. The flash memory can be accessible to multiple storage servers in a storage cluster. To reduce variability in read latency, each flash device provides its status (“busy” or not) to the data layout engine. The data layout engine uses RAID data reconstruction to avoid having to read from a busy flash device.
    Type: Grant
    Filed: November 4, 2011
    Date of Patent: December 31, 2013
    Assignee: NetApp, Inc.
    Inventors: Steve C. Miller, Jeffrey S. Kimmel
  • Publication number: 20130282988
    Abstract: In a computing system, cache coherency is performed by selecting one of a plurality of coherency protocols for a first memory transaction. Each of the plurality of coherency protocols has a unique set of cache states that may be applied to cached data for the first memory transaction. Cache coherency is performed on appropriate caches in the computing system by applying the set of cache states of the selected one of the plurality of coherency protocols.
    Type: Application
    Filed: March 18, 2013
    Publication date: October 24, 2013
    Inventors: Steve C. Miller, Martin M. Deneroff, Kenneth C. Yeager
  • Patent number: 8478835
    Abstract: The data path in a network storage system is streamlined by sharing a memory among multiple functional modules (e.g., N-module and D-module) of a storage server that facilitates symmetric access to data from multiple clients. The shared memory stores data from clients or storage devices to facilitate communication of data between clients and storage devices and/or between functional modules, and reduces redundant copies necessary for data transport. It reduces latency and improves throughput efficiencies by minimizing data copies and using hardware assisted mechanisms such as DMA directly from host bus adapters over an interconnection, e.g. switched PCI-e “network”. This scheme is well suited for a “SAN array” architecture, but also can be applied to NAS protocols or in a unified protocol-agnostic storage system. The storage system can provide a range of configurations ranging from dual module to many modules with redundant switched fabrics for I/O, CPU, memory, and disk connectivity.
    Type: Grant
    Filed: July 17, 2008
    Date of Patent: July 2, 2013
    Assignee: NetApp. Inc.
    Inventors: Jeffrey S. Kimmel, Steve C. Miller, Ashish Prakash
  • Patent number: 8074021
    Abstract: A network storage system includes “raw” flash memory, and storage of data in that flash memory is controlled by an external, log structured, write out-of-place data layout engine of a storage server. By avoiding a separate, onboard data layout engine on the flash devices, the latency associated with operation of such a data layout engine is also avoided. The flash memory can be used as the main persistent storage of a storage server and/or as buffer cache of a storage server, or both. The flash memory can be accessible to multiple storage servers in a storage cluster. To reduce variability in read latency, each flash device provides its status (“busy” or not) to the data layout engine. The data layout engine uses RAID data reconstruction to avoid having to read from a busy flash device.
    Type: Grant
    Filed: March 27, 2008
    Date of Patent: December 6, 2011
    Assignee: NetApp, Inc.
    Inventors: Steve C. Miller, Jeffrey S. Kimmel
  • Patent number: 7945752
    Abstract: A technique for achieving consistent read latency from an array of non-volatile solid-state memories involves an external entity determining the “busy” or “not busy” status of non-volatile solid-state memory elements in a RAID group. An external data layout engine then uses parity based RAID data reconstruction to avoid having to read from any memory element that is busy in a RAID group, along with careful scheduling of writes and erasures.
    Type: Grant
    Filed: March 27, 2008
    Date of Patent: May 17, 2011
    Assignee: NetApp, Inc.
    Inventors: Steve C. Miller, Jeffrey S. Kimmel
  • Publication number: 20100017496
    Abstract: The data path in a network storage system is streamlined by sharing a memory among multiple functional modules (e.g., N-module and D-module) of a storage server that facilitates symmetric access to data from multiple clients. The shared memory stores data from clients or storage devices to facilitate communication of data between clients and storage devices and/or between functional modules, and reduces redundant copies necessary for data transport. It reduces latency and improves throughput efficiencies by minimizing data copies and using hardware assisted mechanisms such as DMA directly from host bus adapters over an interconnection, e.g. switched PCI-e “network”. This scheme is well suited for a “SAN array” architecture, but also can be applied to NAS protocols or in a unified protocol-agnostic storage system. The storage system can provide a range of configurations ranging from dual module to many modules with redundant switched fabrics for I/O, CPU, memory, and disk connectivity.
    Type: Application
    Filed: July 17, 2008
    Publication date: January 21, 2010
    Applicant: NetApp, Inc.
    Inventors: Jeffrey S. Kimmel, Steve C. Miller, Ashish Prakash
  • Publication number: 20090292861
    Abstract: A network storage controller uses a non-volatile solid-state memory (NVSSM) subsystem which includes raw flash memory as stable storage for data, and uses remote direct memory access (RDMA) to access the NVSSM subsystem, including to access the flash memory. Storage of data in the NVSSM subsystem is controlled by an external storage operating system in the storage controller. The storage operating system uses scatter-gather lists to specify the RDMA read and write operations. Multiple client-initiated reads or writes can be combined in the storage controller into a single RDMA read or write, respectively, which can then be decomposed and executed as multiple reads or writes, respectively, in the NVSSM subsystem. Memory accesses generated by a single RDMA read or write may be directed to different memory devices in the NVSSM subsystem, which may include different forms of non-volatile solid-state memory.
    Type: Application
    Filed: July 1, 2008
    Publication date: November 26, 2009
    Applicant: NetApp, Inc.
    Inventors: Arkady Kanevsky, Steve C. Miller