Abstract: An architecture for high-performance flip-flops having minimal clock-activated transistors is disclosed. The flip-flops operating in a first voltage domain can receive an input signal from a second voltage domain. The flip-flops include a first latch electrically coupled to a second latch. The first latch includes a first output and a second output. The second latch further includes a first and a second keeper pull-up sub-circuit which electrically couples to the first and second output of the first latch. The clock-gating functionality of the first and second keeper pull-up sub-circuits is merged with the first latch to reduce the loading on the clock signal, and thus the operation of the flip-flop is contention-free and fully-static. An embodiment of the second latch includes only one clock-activated transistor for low-power application. Another embodiment includes two clock-activated transistors for high-speed application.

Abstract: Circuits, methods, and systems for generating data outputs based on sampled data inputs. One circuit includes a first clock-activated transistor electrically coupled to a first shared clock node, a second clock-activated transistor coupled to a second shared clock node, a third clock-activated transistor coupled to a third shared clock node, a plurality of flip-flops, a latch electrically coupled to the second shared clock node and the third shared clock node, and a first keeper sub-circuit electrically coupled to the third shared clock node and at least one of a first output or a second output of the latch. Each flip-flop of the plurality of flip-flops includes a latch electrically coupled to the second shared clock node and the third shared clock node and a first keeper sub-circuit electrically coupled to the third shared clock node and at least one of a first output or a second output of the latch.

Abstract: A latch circuit comprising a tristate driver and a storage feedback loop and having minimal circuit elements is disclosed. The tristate driver and feedback loop couple to internal nodes of a separate latch circuit to reduce total circuit element count by collapsing elements with common functionality into a single circuit element. The latch circuit presents only one transistor gate load to a clock signal, and the output of the separate latch is coupled to the input of the latch circuit to form a flip-flop. The flip-flop generates an output signal based on a received input signal when the clock signal is at second level and stores the received input signal when the clock signal is at first level. The flip-flop is fully static, contention-free, with near-zero setup time, with less circuit elements than prior arts, and can be configured to integrate multi-input logic functions.

Abstract: Circuits, methods, and systems for generating data outputs based on sampled data inputs. One circuit includes a first latch including a first logic gate, a second logic gate, and a first keeper subcircuit. The circuit further includes a second latch including a third logic gate, a fourth logic gate, and a second keeper subcircuit. The first keeper subcircuit being electrically coupled via a first shared node of the first latch and the second latch, and the second keeper subcircuit being electrically coupled via a second shared node of the first latch and the second latch.