Abstract: A method that decodes serially received MPEG variable length codes by executing instructions in parallel. The method includes an execution unit which includes multiple pipelined functional units. The functional units execute at least two of the instructions in parallel. The instructions utilize and share general purpose. registers. The general purpose. registers store information used by at least two of the instructions.

Abstract: The present invention relates to the use of solid free form fabrication (SFF) technology in the manufacture of impeller blades. The impeller blades may be metal plated and further incorporated onto a rigid skeletal frame to allow for more desirable wear resistance and strength.

Abstract: A method implemented on a data processing device is described comprising: generating supplemental data defining one or more characteristics of one or more light-emitting diodes (“LEDs”) on the data processing device; embedding the supplemental data within a musical instrument digital interface (“MIDI”) stream; decoding the supplemental data concurrently with decoding the MIDI stream; and modifying the one or more characteristics of one or more of the LEDs responsive to decoding the supplemental data.

Abstract: The present invention relates to the use of solid freeform fabrication (SFF) technology in the manufacture of impeller blades. The impeller blades may be metal plated and further incorporated onto a rigid skeletal frame to allow for more desirable wear resistance and strength.

Abstract: In accordance with the present invention, an adder tree structure includes at least two adder stages. In the circuit and method according to the present invention, the first of the two adder stages generates two bits of a common weight and other more significant bits of a weight one bit more significant than the two bits of the common weight. The second of the two adder stages includes an adder that receives the more significant bits generated in the first of the two adder stages. The second adder stage also includes an AND gate which receives and logically AND's the two bits of the common weight to generate a carry-in bit for the adder in the second stage. The above adder tree structure and adding method have an advantage of permitting more input terminals of adders to contain information about the input values to the adder tree structure. Therefore, the adders are used more efficiently and less adders are required to perform a specific function.