Patents by Inventor Steve Kuo

Steve Kuo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11502249
    Abstract: A re-writeable non-volatile memory device including a re-writeable non-volatile two-terminal memory element (ME) having tantalum. The ME including a first terminal, a second terminal, a first layer of a conductive metal oxide (CMO), and a second layer in direct contact with the first layer. The second layer and the first layer being operative to store at least one-bit of data as a plurality of resistive states, and the first and second layer are electrically in series with each other and with the first and second terminals.
    Type: Grant
    Filed: September 22, 2020
    Date of Patent: November 15, 2022
    Assignee: Hefei Reliance Memory Limited
    Inventors: Christophe J. Chevallier, Steve Kuo-Ren Hsia, Wayne Kinney, Steven Longcor, Darrell Rinerson, John Sanchez, Philip F. S. Swab, Edmond R. Ward
  • Publication number: 20210013262
    Abstract: A re-writeable non-volatile memory device including a re-writeable non-volatile two-terminal memory element (ME) having tantalum. The ME including a first terminal, a second terminal, a first layer of a conductive metal oxide (CMO), and a second layer in direct contact with the first layer. The second layer and the first layer being operative to store at least one-bit of data as a plurality of resistive states, and the first and second layer are electrically in series with each other and with the first and second terminals.
    Type: Application
    Filed: September 22, 2020
    Publication date: January 14, 2021
    Inventors: Christophe J. CHEVALLIER, Steve Kuo-Ren HSIA, Wayne KINNEY, Steven LONGCOR, Darrell RINERSON, John SANCHEZ, Philip F.S. SWAB, Edmond R. WARD
  • Patent number: 10833125
    Abstract: A re-writeable non-volatile memory device including a re-writeable non-volatile two-terminal memory element (ME) having tantalum. The ME including a first terminal, a second terminal, a first layer of a conductive metal oxide (CMO), and a second layer in direct contact with the first layer. The second layer and the first layer being operative to store at least one-bit of data as a plurality of resistive states, and the first and second layer are electrically in series with each other and with the first and second terminals.
    Type: Grant
    Filed: May 14, 2019
    Date of Patent: November 10, 2020
    Assignee: Hefei Reliance Memory Limited
    Inventors: Christophe J. Chevallier, Steve Kuo-Ren Hsia, Wayne Kinney, Steven Longcor, Darrell Rinerson, John Sanchez, Philip F. S. Swab, Edmond R. Ward
  • Patent number: 10797106
    Abstract: A re-writeable non-volatile memory device including a re-writeable non-volatile two-terminal memory element (ME) having tantalum. The ME including a first terminal, a second terminal, a first layer of a conductive metal oxide (CMO), and a second layer in direct contact with the first layer. The second layer and the first layer being operative to store at least one-bit of data as a plurality of resistive states, and the first and second layer are electrically in series with each other and with the first and second terminals.
    Type: Grant
    Filed: May 14, 2019
    Date of Patent: October 6, 2020
    Assignee: Hefei Reliance Memory Limited
    Inventors: Christophe J. Chevallier, Steve Kuo-Ren Hsia, Wayne Kinney, Steven Longcor, Darrell Rinerson, John Sanchez, Philip F. S. Swab, Edmond R. Ward
  • Publication number: 20190305047
    Abstract: A re-writeable non-volatile memory device including a re-writeable non-volatile two-terminal memory element (ME) having tantalum. The ME including a first terminal, a second terminal, a first layer of a conductive metal oxide (CMO), and a second layer in direct contact with the first layer. The second layer and the first layer being operative to store at least one-bit of data as a plurality of resistive states, and the first and second layer are electrically in series with each other and with the first and second terminals.
    Type: Application
    Filed: May 14, 2019
    Publication date: October 3, 2019
    Inventors: Christophe J. CHEVALLIER, Steve Kuo-Ren HSIA, Wayne KINNEY, Steven LONGCOR, Darrell RINERSON, John SANCHEZ, Philip F.S. SWAB, Edmond R. WARD
  • Patent number: 10340312
    Abstract: A re-writeable non-volatile memory device including a re-writeable non-volatile two-terminal memory element (ME) having tantalum. The ME including a first terminal, a second terminal, a first layer of a conductive metal oxide (CMO), and a second layer in direct contact with the first layer. The second layer and the first layer being operative to store at least one-bit of data as a plurality of resistive states, and the first and second layer are electrically in series with each other and with the first and second terminals.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: July 2, 2019
    Assignee: Hefei Reliance Memory Limited
    Inventors: Christophe J. Chevallier, Steve Kuo-Ren Hsia, Wayne Kinney, Steven Longcor, Darrell Rinerson, John Sanchez, Philip F. S. Swab, Edmond R. Ward
  • Publication number: 20180122857
    Abstract: A re-writeable non-volatile memory device including a re-writeable non-volatile two-terminal memory element (ME) having tantalum. The ME including a first terminal, a second terminal, a first layer of a conductive metal oxide (CMO), and a second layer in direct contact with the first layer. The second layer and the first layer being operative to store at least one-bit of data as a plurality of resistive states, and the first and second layer are electrically in series with each other and with the first and second terminals.
    Type: Application
    Filed: October 30, 2017
    Publication date: May 3, 2018
    Inventors: Christophe J. Chevallier, Steve Kuo-Ren Hsia, Wayne Kinney, Steven Longcor, Darrell Rinerson, John Sanchez, Philip F.S. Swab, Edmond R. Ward
  • Patent number: 9806130
    Abstract: A re-writeable non-volatile memory device including a re-writeable non-volatile two-terminal memory element (ME) having tantalum. The ME including a first terminal, a second terminal, a first layer of a conductive metal oxide (CMO), and a second layer in direct contact with the first layer. The second layer and the first layer being operative to store at least one-bit of data as a plurality of resistive states, and the first and second layer are electrically in series with each other and with the first and second terminals.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: October 31, 2017
    Assignee: Unity Semiconductor Corporation
    Inventors: Christophe J. Chevallier, Steve Kuo-Ren Hsia, Wayne Kinney, Steven Longcor, Darrell Rinerson, John Sanchez, Philip F. S. Swab, Edmond R. Ward
  • Publication number: 20170179197
    Abstract: A re-writeable non-volatile memory device including a re-writeable non-volatile two-terminal memory element (ME) having tantalum. The ME including a first terminal, a second terminal, a first layer of a conductive metal oxide (CMO), and a second layer in direct contact with the first layer. The second layer and the first layer being operative to store at least one-bit of data as a plurality of resistive states, and the first and second layer are electrically in series with each other and with the first and second terminals.
    Type: Application
    Filed: December 29, 2016
    Publication date: June 22, 2017
    Inventors: Christophe J. Chevallier, Steve Kuo-Ren Hsia, Wayne Kinney, Steven Longcor, Darrell Rinerson, John Sanchez, Philip F.S. Swab, Edmond R. Ward
  • Patent number: 9570515
    Abstract: A memory cell including conductive oxide electrodes is disclosed. The memory cell includes a memory element operative to store data as a plurality of resistive states. The memory element includes a layer of a conductive metal oxide (CMO) (e.g., a perovskite) in contact with an electrode that may comprise one or more layers of material. At least one of those layers of material can be a conductive oxide (e.g., a perovskite such as LaSrCoO3-LSCoO or LaNiO3-LNO) that is in contact with the CMO. The conductive oxide layer can be selected as a seed layer operative to provide a good lattice match with and/or a lower crystallization temperature for the CMO. The conductive oxide layer may also be in contact with a metal layer (e.g., Pt). The memory cell additionally exhibits non-linear IV characteristics, which can be favorable in certain arrays, such as non-volatile two-terminal cross-point memory arrays.
    Type: Grant
    Filed: September 10, 2015
    Date of Patent: February 14, 2017
    Assignee: UNITY SEMICONDUCTOR CORPORATION
    Inventors: Christophe J. Chevallier, Steve Kuo-Ren Hsia, Wayne Kinney, Steven Longcor, Darrell Rinerson, John Sanchez, Philip F. S. Swab, Edmond R. Ward
  • Patent number: 9418693
    Abstract: An embodiment of the invention relates to a perpendicular magnetic recording medium comprising (1) a substrate, (2) an interlayer comprising hexagonal columns and (3) a magnetic layer, wherein the magnetic layer is deposited applying a bias voltage to the substrate such that the magnetic layer comprises magnetic grains having substantially no sub-grains within the magnetic layer, and the magnetic layer has perpendicular magnetic anisotropy.
    Type: Grant
    Filed: March 30, 2015
    Date of Patent: August 16, 2016
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Weilu Xu, Miaogen Lu, Mariana Rodica Munteanu, Michael Z. Wu, Shanghsien A. Rou, Steve Kuo-Hsing Hwang, Edward T. Yen
  • Publication number: 20160005793
    Abstract: A memory cell including conductive oxide electrodes is disclosed. The memory cell includes a memory element operative to store data as a plurality of resistive states. The memory element includes a layer of a conductive metal oxide (CMO) (e.g., a perovskite) in contact with an electrode that may comprise one or more layers of material. At least one of those layers of material can be a conductive oxide (e.g., a perovskite such as LaSrCoO3-LSCoO or LaNiO3-LNO) that is in contact with the CMO. The conductive oxide layer can be selected as a seed layer operative to provide a good lattice match with and/or a lower crystallization temperature for the CMO. The conductive oxide layer may also be in contact with a metal layer (e.g., Pt). The memory cell additionally exhibits non-linear IV characteristics, which can be favorable in certain arrays, such as non-volatile two-terminal cross-point memory arrays.
    Type: Application
    Filed: September 10, 2015
    Publication date: January 7, 2016
    Inventors: Christophe J. Chevallier, Steve Kuo-Ren Hsia, Wayne Kinney, Steven Longcor, Darrell Rinerson, John Sanchez, Philip F.S. Swab, Edmond R. Ward
  • Patent number: 9159408
    Abstract: A memory cell including conductive oxide electrodes is disclosed. The memory cell includes a memory element operative to store data as a plurality of resistive states. The memory element includes a layer of a conductive metal oxide (CMO) (e.g., a perovskite) in contact with an electrode that may comprise one or more layers of material. At least one of those layers of material can be a conductive oxide (e.g., a perovskite such as LaSrCoO3-LSCoO or LaNiO3-LNO) that is in contact with the CMO. The conductive oxide layer can be selected as a seed layer operative to provide a good lattice match with and/or a lower crystallization temperature for the CMO. The conductive oxide layer may also be in contact with a metal layer (e.g., Pt). The memory cell additionally exhibits non-linear IV characteristics, which can be favorable in certain arrays, such as non-volatile two-terminal cross-point memory arrays.
    Type: Grant
    Filed: January 29, 2014
    Date of Patent: October 13, 2015
    Assignee: UNITY SEMICONDUCTOR CORPORATION
    Inventors: Christophe J. Chevallier, Steve Kuo-Ren Hsia, Wayne Kinney, Steven Longcor, Darrell Rinerson, John Sanchez, Philip F. S. Swab, Edmond R. Ward
  • Publication number: 20150279400
    Abstract: An embodiment of the invention relates to a perpendicular magnetic recording medium comprising (1) a substrate, (2) an interlayer comprising hexagonal columns and (3) a magnetic layer, wherein the magnetic layer is deposited applying a bias voltage to the substrate such that the magnetic layer comprises magnetic grains having substantially no sub-grains within the magnetic layer, and the magnetic layer has perpendicular magnetic anisotropy.
    Type: Application
    Filed: March 30, 2015
    Publication date: October 1, 2015
    Inventors: Weilu Xu, Miaogen Lu, Mariana Rodica Munteanu, Michael Z. Wu, Shanghsien A. Rou, Steve Kuo-Hsing Hwang, Edward T. Yen
  • Patent number: 8993073
    Abstract: An embodiment of the invention relates to a perpendicular magnetic recording medium comprising (1) a substrate, (2) an interlayer comprising hexagonal columns and (3) a magnetic layer, wherein the magnetic layer is deposited applying a bias voltage to the substrate such that the magnetic layer comprises magnetic grains having substantially no sub-grains within the magnetic layer, and the magnetic layer has perpendicular magnetic anisotropy.
    Type: Grant
    Filed: July 14, 2008
    Date of Patent: March 31, 2015
    Assignee: Seagate Technology LLC
    Inventors: Weilu Xu, Miaogen Lu, Mariana R. Munteanu, Michael Z. Wu, Shanghsien Alex Rou, Steve Kuo-Hsing Hwang, Ed Yen
  • Publication number: 20140211542
    Abstract: A memory cell including conductive oxide electrodes is disclosed. The memory cell includes a memory element operative to store data as a plurality of resistive states. The memory element includes a layer of a conductive metal oxide (CMO) (e.g., a perovskite) in contact with an electrode that may comprise one or more layers of material. At least one of those layers of material can be a conductive oxide (e.g., a perovskite such as LaSrCoO3-LSCoO or LaNiO3-LNO) that is in contact with the CMO. The conductive oxide layer can be selected as a seed layer operative to provide a good lattice match with and/or a lower crystallization temperature for the CMO. The conductive oxide layer may also be in contact with a metal layer (e.g., Pt). The memory cell additionally exhibits non-linear IV characteristics, which can be favorable in certain arrays, such as non-volatile two-terminal cross-point memory arrays.
    Type: Application
    Filed: January 29, 2014
    Publication date: July 31, 2014
    Applicant: Unity Semiconductor Corporation
    Inventors: Christophe J. Chevallier, Steve Kuo-Ren Hsia, Wayne Kinney, Steven Longcor, Darrell Rinerson, John Sanchez, Philip F.S. Swab, Edmond R. Ward
  • Patent number: 8675389
    Abstract: A memory cell including conductive oxide electrodes is disclosed. The memory cell includes a memory element operative to store data as a plurality of resistive states. The memory element includes a layer of a conductive metal oxide (CMO) (e.g., a perovskite) in contact with an electrode that may comprise one or more layers of material. At least one of those layers of material can be a conductive oxide (e.g., a perovskite such as LaSrCoO3—LSCoO or LaNiO3—LNO) that is in contact with the CMO. The conductive oxide layer can be selected as a seed layer operative to provide a good lattice match with and/or a lower crystallization temperature for the CMO. The conductive oxide layer may also be in contact with a metal layer (e.g., Pt). The memory cell additionally exhibits non-linear IV characteristics, which can be favorable in certain arrays, such as non-volatile two-terminal cross-point memory arrays.
    Type: Grant
    Filed: October 13, 2011
    Date of Patent: March 18, 2014
    Assignee: Unity Semiconductor Corporation
    Inventors: Christophe Chevallier, Steve Kuo-Ren Hsia, Wayne Kinney, Steven Longcor, Darrell Rinerson, John Sanchez, Jr., Philip Swab, Edmond Ward
  • Patent number: 8611130
    Abstract: A treated conductive element is provided. A conductive element can be treated by depositing either a reactive metal or a very thin layer of material on the conductive element. The reactive metal (or very thin layer of material) would typically be sandwiched between the conductive element and an electrode. The structure additionally exhibits non-linear IV characteristics, which can be favorable in certain arrays.
    Type: Grant
    Filed: November 21, 2011
    Date of Patent: December 17, 2013
    Assignee: Unity Semiconductor Corporation
    Inventors: Darrell Rinerson, Christophe Chevallier, Steve Kuo-Ren Hsia, Wayne Kinney, Steven Longcor, John Sanchez, Jr., Philip Swab, Edmond Ward
  • Publication number: 20120064691
    Abstract: A treated conductive element is provided. A conductive element can be treated by depositing either a reactive metal or a very thin layer of material on the conductive element. The reactive metal (or very thin layer of material) would typically be sandwiched between the conductive element and an electrode. The structure additionally exhibits non-linear IV characteristics, which can be favorable in certain arrays.
    Type: Application
    Filed: November 21, 2011
    Publication date: March 15, 2012
    Applicant: UNITY SEMICONDUCTOR CORPORATION
    Inventors: DARRELL RINERSON, WAYNE KINNEY, EDMOND R. WARD, STEVE KUO-REN HSIA, STEVEN W. LONGCOR, CHRISTOPHE J. CHEVALLIER, JOHN SANCHEZ, PHILIP F. S. SWAB
  • Publication number: 20120033481
    Abstract: A memory cell including conductive oxide electrodes is disclosed. The memory cell includes a memory element operative to store data as a plurality of resistive states. The memory element includes a layer of a conductive metal oxide (CMO) (e.g., a perovskite) in contact with an electrode that may comprise one or more layers of material. At least one of those layers of material can be a conductive oxide (e.g., a perovskite such as LaSrCoO3—LSCoO or LaNiO3—LNO) that is in contact with the CMO. The conductive oxide layer can be selected as a seed layer operative to provide a good lattice match with and/or a lower crystallization temperature for the CMO. The conductive oxide layer may also be in contact with a metal layer (e.g., Pt). The memory cell additionally exhibits non-linear IV characteristics, which can be favorable in certain arrays, such as non-volatile two-terminal cross-point memory arrays.
    Type: Application
    Filed: October 13, 2011
    Publication date: February 9, 2012
    Applicant: UNITY SEMICONDUCTOR CORPORATION
    Inventors: DARRELL RINERSON, WAYNE KINNEY, EDMOND R. WARD, STEVE KUO-REN HSIA, STEVEN LONGCOR, CHRISTOPHE J. CHEVALLIER, JOHN SANCHEZ, PHILIP F. S. SWAB