Abstract: A computer system optimized for real-time applications which provides increased performance over current computer architectures. The system includes a standard local system bus, such as the PCI bus, and also includes a dedicated real-time bus or multimedia bus. Thus multimedia devices such as video cards, audio cards, etc., as well as communications devices, transfer real-time data through a separate bus without requiring arbitration for the PCI bus. The computer system of the present invention thus provides much greater performance for real-time applications than prior systems. In various embodiments, multimedia devices transmit addressing and control information for a multimedia bus transfer either over the PCI bus or using a separate serial control channel. The multimedia bus may also comprise separate multimedia channels for different data types. In various embodiments, methods transfer periodic multimedia data over the multimedia bus.

Abstract: A computer system including a plurality of multimedia devices each having a high-speed memory data channel for accessing system memory. Each multimedia device has a high speed link directly to system memory, which is preferably single or multiple ported memory. These individual links are preferably high speed serial interconnects but, alternatively, may be 4-bit, 8-bit, 16-bit, 24-bit, 32-bit, 64-bit or any combination thereof. In this embodiment, intelligent buffering is preferably implemented within the core logic, and arbitration for access to main memory is preferably implemented within the core logic. Each of the multimedia devices uses its dedicated memory data channel to perform data accesses and transfers directly to the main memory, bypassing PCI bus arbitration and PCI bus cycles. Alternatively, each of the multimedia devices includes a high speed memory channel directly to the memory controller in the core logic for accessing system memory.

Abstract: An integrated processor includes CPU core, cache memory, and cache controller coupled to a local bus via a local bus interface. The integrated processor further includes memory controller for coupling system memory to the local bus, and a bus interface unit for coupling external peripheral devices to the local bus. The cache controller includes an address tag and state logic circuit which keeps track of a physical address in system memory which corresponds to each entry within cache memory. Address tag and state logic circuit contains state information that indicates whether each cache line is valid and/or dirty. The cache controller includes a snoop control circuit which monitors the local bus to determine whether a memory cycle has been executed by an alternate bus master. During such a memory cycle of an alternate bus master, a comparator circuit determines whether a cache hit has occurred.

Abstract: An improved means and method for expanded memory system access and control is disclosed. A logic array in the expanded memory control circuitry which accesses and controls up to two separate expansion boards through the use of static random access memory as register circuits and octal buffers for addressing. The control and access method implemented through a state machine in the logic array provides the operation of the improved expanded memory system to control additional expansion boards and to access the appropriate memory locations.