Abstract: Various apparatuses, methods and systems for creating an integrated circuit and performing a gate level simulation of a circuit are disclosed herein. For example, some embodiments of the present invention provide a system for performing a gate level simulation of a circuit including a computer system, a design verification tool and an output device. The design verification tool, executable on the computer system, includes a simulator and a partial timing model generator. The partial timing model generator is operable to generate a representation of the circuit for simulation by cutting a first portion of a circuit out of a full gate level netlist for the circuit and leaving a second portion of the circuit represented by the full gate level netlist, and to overlay a simplified representation of the first portion of the circuit over the representation of the circuit. The first portion of the circuit is cut out at timing paths.

Abstract: Various apparatuses, methods and systems for creating an integrated circuit and performing a gate level simulation of a circuit are disclosed herein. For example, some embodiments of the present invention provide a system for performing a gate level simulation of a circuit including a computer system, a design verification tool and an output device. The design verification tool, executable on the computer system, includes a simulator and a partial timing model generator. The partial timing model generator is operable to generate a representation of the circuit for simulation by cutting a first portion of a circuit out of a full gate level netlist for the circuit and leaving a second portion of the circuit represented by the full gate level netlist, and to overlay a simplified representation of the first portion of the circuit over the representation of the circuit. The first portion of the circuit is cut out at timing paths.