Abstract: An analog delay locked loop for receiving a reference clock signal and for generating a delayed output clock signal includes a voltage controlled delay line, a fixed delay line, a delay voltage control, a fast/slow latch, a phase detector, as well as reset and clock off circuits. The fast/slow latch generates three signals that are received by the delay voltage control: a “latched slow signal”, a “latched fast signal”, as well as a “latched fast to slow signal”. The phase detector generates “go fast” and “go slow” signals that are received by the fast/slow latch. The analog delay locked loop sets the initial delay of the delay line at or near its minimum value on start-up. The delay is then forced to increase from the minimum value until a locking condition is achieved independent of the phase relationship between the reference and delayed clock signals.

Abstract: A limited output address register technique for selectively variable write latency in double data rate 2 (DDR2) integrated circuit memory devices providing a reduced number of paths directly connected to the output. A chain of DQ flip-flops is disclosed which is only loaded on valid write address commands but shifts continually thereafter every clock cycle. Since new READ or WRITE commands cannot be issued on successive cycles, at any given point in the chain an address (or state) is valid for at least two cycles. Therefore, a selected point in the register chain can be used to satisfy the requirements for two different latencies. For DDR2, having N write latency cases, only ceil(N/2) access points to the write address output have to be provided thereby saving on-chip area and increasing speed. In a specific embodiment disclosed, DDR1 may also be supported.

Abstract: Data bits are prefetched from memory cells in parallel and are read out serially. The memory includes multiple stages (1710) of latches through which the parallel data is transferred before being read out serially. The multiple stages provide suitable delays to satisfy variable latency requirements (e.g. CAS latency in DDR2). The first bit for the serial output bypasses the last stage (1710.M). In some embodiments, the control signals controlling the stages other than the last stage in their providing the first data bit to the memory output are not functions of the control signals controlling the last stage providing the subsequent data bits to the memory output.

Abstract: A sorting circuit (140) transfers data between a first group of at least four lines (134) on which the data items are arranged based on their addresses, and a second group of lines (138, WD0R, WD0F, WD1R, WD1F) on which the data items are arranged based on the order in which they are read or written in a burst operation. Six signals (SORT) and their complements are sufficient to control the sorting circuit for both the read and the write operations, and provide both the DDR and the DDR2 functionality.

Abstract: A memory performs a hidden refresh only at the end of a read operation or when the memory is disabled but is supposed to retain data in the disabled state. When the memory is in the enabled state, the refresh is not performed at the end of any operation other than read. This is done to ensure that execution of any memory access command will not be delayed by a refresh as long as the user follows certain timing rules. Other embodiments arc also provided.

Abstract: A memory performs a hidden refresh only at the end of a read operation or when the memory is disabled but is supposed to retain data in the disabled state. When the memory is in the enabled state, the refresh is not performed at the end of any operation other than read. This is done to ensure that execution of any memory access command will not be delayed by a refresh as long as the user follows certain timing rules. Other embodiments are also provided.