Abstract: A battery includes a stacked arrangement of electrochemical cells. Each electrochemical cell is free of a cell housing and includes a bipolar plate having a substrate, a first active material layer formed on a first surface of the substrate, and a second active material layer formed on a second surface of the substrate. Each cell includes a solid electrolyte layer that encapsulates at least one of the active material layers, and an edge insulating device that is disposed between the peripheral edges of the substrates of each pair of adjacent cells. A support frame surrounds the cell stack and is configured to receive and support the outer peripheral edge of the edge insulating device of each cell.

Abstract: A preheat burner assembly and method for preheating forming dies includes a frame, a burner manifold and a link assembly. The burner manifold as a plurality of burner orifices for preheating the forming dies. The burner manifold is connected to a fuel source. The link assembly mounts the burner manifold to the frame for movement between a stowed position and a deployed position. The burner is moved via the link assembly to a deployed position for preheating the forming dies. The forming dies are preheated. The burner manifold is subsequently moved via the link assembly from the deployed position to an upright stowed position.

Abstract: A preheat burner assembly and method for preheating forming dies includes a frame, a burner manifold and a link assembly. The burner manifold as a plurality of burner orifices for preheating the forming dies. The burner manifold is connected to a fuel source. The link assembly mounts the burner manifold to the frame for movement between a stowed position and a deployed position. The burner is moved via the link assembly to a deployed position for preheating the forming dies. The forming dies are preheated. The burner manifold is subsequently moved via the link assembly from the deployed position to an upright stowed position.

Abstract: In an embodiment, a non-volatile memory array wherein narrow word lines, as small as the minimum feature size width F, in separate strings, are extended outwardly from a non-volatile memory array and joined by wider connector segments. The joined word lines provide new opportunities. First, metal straps that can be formed to overlie the word lines can be joined by metal connector segments to the word lines. The connector segments can serve as an interface between the polysilicon word lines and the metal straps. Two adjacent word lines in the same string share a single metal strap using these segments thereby reducing the overall number of segments and contacts in the array. Increased width of the polysilicon joinder segments joining word lines in different strings, provides the opportunity for widening the connection beyond the minimum feature size so that contact may be readily made between the metal straps and the polysilicon word lines. Second, the joined word lines require fewer row decoder circuits.

Abstract: In an embodiment, a non-volatile memory array wherein narrow word lines, as small as the minimum feature size width F, in separate strings, are extended outwardly from a non-volatile memory array and joined by wider connector segments. The joined word lines provide new opportunities. First, metal straps that can be formed to overlie the word lines can be joined by metal connector segments to the word lines. The connector segments can serve as an interface between the polysilicon word lines and the metal straps. Two adjacent word lines in the same string share a single metal strap using these segments thereby reducing the overall number of segments and contacts in the array. Increased width of the polysilicon joinder segments joining word lines in different strings, provides the opportunity for widening the connection beyond the minimum feature size so that contact may be readily made between the metal straps and the polysilicon word lines. Second, the joined word lines require fewer row decoder circuits.

Abstract: In a flash memory array, an internal refresh periodically rewrites the information stored in each of the rows of memory cells in a flash memory. The flash memory array includes a refresh pointer bitline that indicates the row to be refreshed. In a first embodiment of the present invention, the internal refresh is performed automatically after every user erase/program cycle. In second and third embodiments, the user of the of the flash memory array selects when the internal refresh is performed, but the address of the row to be refreshed is supplied internally. In each of the three the embodiments, the internal refresh includes the four operations of SCAN, REFRESH ERASE, REFRESH PROGRAM, and INCREMENT.

Abstract: In a flash memory array, an internal refresh periodically rewrites the information stored in each of the rows of memory cells in a flash memory. The flash memory array includes a refresh pointer bitline that indicates the row to be refreshed. In a first embodiment of the present invention, the internal refresh is performed automatically after every user erase/program cycle. In second and third embodiments, the user of the of the flash memory array selects when the internal refresh is performed, but the address of the row to be refreshed is supplied internally. In each of the three the embodiments, the internal refresh includes the four operations of SCAN, REFRESH ERASE, REFRESH PROGRAM, and INCREMENT.

Abstract: An integrated circuit device which includes a memory array comprising a plurality of respective memory locations for storing binary data, each respective memory location corresponding to a respective combination of binary address signals, the device further comprising: at least two respective ports for receiving respective combinations of binary address signals corresponding to respective locations of said memory array; transition detection and signal providing circuitry for detecting a change in a respective binary address signal combination received by either a first or second of the at least two ports and for providing a first transition signal in response to a change in a respective first combination of binary address signals received by the first port and for providing a second respective transition signal in response to a change in a respective second combination of binary address signals received by the second port; and contention detection and signal providing means for receiving the first and the sec