Abstract: A single integrated circuit including programmable logic having a plurality of inputs and a plurality of outputs, with at least one input of the programmable logic coupled to an on-chip analog comparator is provided. In one aspect of the invention, a voltage comparator having programmable hysteresis for setting the output state switching thresholds of the comparator is utilized. In another aspect of the invention, the programmable logic comprises a programmable combinatorial array having a programmable AND array and a fixed OR array. The integrated circuit further comprises an output block including a plurality of flip-flops and output buffers coupled to at least one I/O pin for selectively determining the state of the I/O pin. In yet another aspect the invention, the programmable combinatorial array includes a plurality of AND array outputs, divided into three subsets, for input to three pairs of OR gates which comprise the fixed OR plane of the device.