Patents by Inventor Steve W. Heppler
Steve W. Heppler has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7998305Abstract: An anisotropic electrically conducting interconnect is disclosed in which an adhesive comprising particles having a breakable coating of at least one electrically nonconductive material is compressed between a first contact and a second contact. Compression to two contacts breaks the breakable coating exposing an electrically conducting material which makes contact with the first and second contacts. The electrically conducting material may be a metal conductor or a two-part reactive conductive resin/catalyst system. Also disclosed are processes for making such electrical interconnects and adhesives for use in making electrical interconnect.Type: GrantFiled: December 19, 2007Date of Patent: August 16, 2011Assignee: Micron Technology, Inc.Inventors: Chad A. Cobbley, Steve W. Heppler
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Patent number: 7829190Abstract: An anisotropic electrically conducting interconnect is disclosed in which an adhesive comprising particles having a breakable coating of at least one electrically nonconductive material is compressed between a first contact and a second contact. Compression to two contacts breaks the breakable coating exposing an electrically conducting material which makes contact with the first and second contacts. The electrically conducting material may be a metal conductor or a two-part reactive conductive resin/catalyst system. Also disclosed are processes for making such electrical interconnects and adhesives for use in making electrical interconnect.Type: GrantFiled: August 25, 2005Date of Patent: November 9, 2010Assignee: Micron Technology, Inc.Inventors: Chad A. Cobbley, Steve W. Heppler
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Patent number: 7326316Abstract: An anisotropic electrically conducting interconnect is disclosed in which an adhesive comprising particles having a breakable coating of at feast one electrically nonconductive material is compressed between a first contact and a second contact. Compression to two contacts breaks the breakable coating exposing an electrically conducting material which makes contact with the first and second contacts. The electrically conducting material may be a metal conductor or a two-part reactive conductive resin/catalyst system. Also disclosed are processes for making such electrical interconnects and adhesives for use in making electrical interconnect.Type: GrantFiled: June 22, 2004Date of Patent: February 5, 2008Assignee: Micron Technology, Inc.Inventors: Chad A. Cobbley, Steve W. Heppler
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Patent number: 6951684Abstract: An anisotropic electrically conducting interconnect is disclosed in which an adhesive comprising particles having a breakable coating of at least one electrically nonconductive material is compressed between a first contact and a second contact. Compression to two contacts breaks the breakable coating exposing an electrically conducting material which makes contact with the first and second contacts. The electrically conducting material may be a metal conductor or a two-part reactive conductive resin/catalyst system. Also disclosed are processes for making such electrical interconnects and adhesives for use in making electrical interconnect.Type: GrantFiled: May 10, 2004Date of Patent: October 4, 2005Assignee: Micron Technology, Inc.Inventors: Chad A. Cobbley, Steve W. Heppler
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Publication number: 20040232391Abstract: An anisotropic electrically conducting interconnect is disclosed in which an adhesive comprising particles having a breakable coating of at least one electrically nonconductive material is compressed between a first contact and a second contact. Compression to two contacts breaks the breakable coating exposing an electrically conducting material which makes contact with the first and second contacts. The electrically conducting material may be a metal conductor or a two-part reactive conductive resin/catalyst system. Also disclosed are processes for making such electrical interconnects and adhesives for use in making electrical interconnect.Type: ApplicationFiled: June 22, 2004Publication date: November 25, 2004Inventors: Chad A. Cobbley, Steve W. Heppler
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Publication number: 20040229032Abstract: An anisotropic electrically conducting interconnect is disclosed in which an adhesive comprising particles having a breakable coating of at feast one electrically nonconductive material is compressed between a first contact and a second contact. Compression to two contacts breaks the breakable coating exposing an electrically conducting material which makes contact with the first and second contacts. The electrically conducting material may be a metal conductor or a two-part reactive conductive resin/catalyst system. Also disclosed are processes for making such electrical interconnects and adhesives for use in making electrical interconnect.Type: ApplicationFiled: June 22, 2004Publication date: November 18, 2004Inventors: Chad A. Cobbley, Steve W. Heppler
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Publication number: 20040209497Abstract: An anisotropic electrically conducting interconnect is disclosed in which an adhesive comprising particles having a breakable coating of at least one electrically nonconductive material is compressed between a first contact and a second contact. Compression to two contacts breaks the breakable coating exposing an electrically conducting material which makes contact with the first and second contacts. The electrically conducting material may be a metal conductor or a two-part reactive conductive resin/catalyst system. Also disclosed are processes for making such electrical interconnects and adhesives for use in making electrical interconnect.Type: ApplicationFiled: May 10, 2004Publication date: October 21, 2004Inventors: Chad A. Cobbley, Steve W. Heppler
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Patent number: 6777071Abstract: An anisotropic electrically conducting interconnect is disclosed in which an adhesive comprising particles having a breakable coating of at least one electrically nonconductive material is compressed between a first contact and a second contact. Compression to two contacts breaks the breakable coating exposing an electrically conducting material which makes contact with the first and second contacts. The electrically conducting material may be a metal conductor or a two-part reactive conductive resin/catalyst system. Also disclosed are processes for making such electrical interconnects and adhesives for use in making electrical interconnect.Type: GrantFiled: April 25, 2002Date of Patent: August 17, 2004Assignee: Micron Technology, Inc.Inventors: Chad A. Cobbley, Steve W. Heppler
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Publication number: 20030203668Abstract: An anisotropic electrically conducting interconnect is disclosed in which an adhesive comprising particles having a breakable coating of at least one electrically nonconductive material is compressed between a first contact and a second contact. Compression to two contacts breaks the breakable coating exposing an electrically conducting material which makes contact with the first and second contacts. The electrically conducting material may be a metal conductor or a two-part reactive conductive resin/catalyst system. Also disclosed are processes for making such electrical interconnects and adhesives for use in making electrical interconnect.Type: ApplicationFiled: April 25, 2002Publication date: October 30, 2003Applicant: Micron Technology, Inc.Inventors: Chad A. Cobbley, Steve W. Heppler
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Patent number: 6371840Abstract: A method and apparatus are provided for handling planar structures, such as semiconductor wafers, with reduced breakage and cracking. The method includes the step of segmenting a wafer prior to grinding. The apparatus includes a segmented vacuum table for supporting wafer portions in position to be ground to a desired thickness. In another aspect of the invention, adhesive material is employed to individually secure wafer portions in position during the grinding process.Type: GrantFiled: June 13, 2000Date of Patent: April 16, 2002Assignee: Micron Technology, Inc.Inventors: Michael B. Ball, Steve W. Heppler
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Patent number: 6351022Abstract: A method and apparatus are provided for handling planar structures, such as semiconductor wafers, with reduced breakage and cracking. The method includes the step of segmenting a wafer prior to grinding. The apparatus includes a segmented vacuum table for supporting wafer portions in position to be ground to a desired thickness. In another aspect of the invention, adhesive material is employed to individually secure wafer portions in position during the grinding process.Type: GrantFiled: November 30, 1999Date of Patent: February 26, 2002Assignee: Micron Technology, Inc.Inventors: Michael B. Ball, Steve W. Heppler
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Patent number: 6120360Abstract: A method and apparatus are provided for handling planar structures, such as semiconductor wafers, with reduced breakage and cracking. The method includes the step of segmenting a wafer prior to grinding. The apparatus includes a segmented vacuum table for supporting wafer portions in position to be ground to a desired thickness. In another aspect of the invention, adhesive material is employed to individually secure wafer portions in position during the grinding process.Type: GrantFiled: May 5, 1999Date of Patent: September 19, 2000Assignee: Micron Technology, Inc.Inventors: Michael B. Ball, Steve W. Heppler
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Patent number: 5920769Abstract: A method and apparatus are provided for handling planar structures, such as semiconductor wafers, with reduced breakage and cracking. The method includes the step of segmenting a wafer prior to grinding. The apparatus includes a segmented vacuum table for supporting wafer portions in position to be ground to a desired thickness. In another aspect of the invention, adhesive material is employed to individually secure wafer portions in position during the grinding process.Type: GrantFiled: December 12, 1997Date of Patent: July 6, 1999Assignee: Micron Technology, Inc.Inventors: Michael B. Ball, Steve W. Heppler
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Patent number: 5348164Abstract: There is an IC (integrated circuit) testing device 11 that receives singulated ICs from a singulation station's bottom table 44, where an IC 15 has slid down onto loading ramp or track 16. The IC will slide into test station 18, where stop pin 22 has been inserted to stop the IC in DUT (device under test) station 20. In the DUT station, the IC is securely held in position by an extractor bar 26, insertion bar 28, and a part guide 24. Thereby, test cite station 18 will move downward and insert IC 15 into testing socket 30. After testing the IC, testing station 18 returns upward with the IC in the same secured position. Pin 22 will be removed to allow the IC to slide into part holding station 31. If the IC was not defective, pin 32 will be removed to allow the IC to slide onto track 36 of the IC separator station 34. While the test cite station 18 is in the up position a second IC is slid along track 16 and loaded into DUT cite 20 being readied for the next test cycle.Type: GrantFiled: April 13, 1993Date of Patent: September 20, 1994Assignee: Micron Semiconductor, Inc.Inventor: Steve W. Heppler
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Patent number: RE38894Abstract: There is an IC (integrated circuit) testing device 11 that receives singulated ICs from a singulation station's bottom table 44, where an IC 15 has slid down onto loading ramp or track 16. The IC will slide into test station 18, where stop pin 22 has been inserted to stop the IC in DUT (device under test) station 20. In the DUT station, the IC is securely held in position by an extractor bar 26, insertion bar 28, and a part guide 24. Thereby, test cite station 18 will move downward and insert IC 15 into testing socket 30. After testing the IC, testing station 18 returns upward with IC in the same secured position. Pin 22 will be removed to allow the IC to slide into part holding station 31. If the IC was not defective, pin 32 will be removed to allow the IC to slide onto track 36 of the IC separator station 34. While the test cite station 18 is in the up position a second IC is slid along track 16 and loaded into DUT cite 20 being readied for the next test cycle.Type: GrantFiled: September 19, 1996Date of Patent: November 29, 2005Assignee: Micron Tehnology, Inc.Inventor: Steve W. Heppler