Abstract: An apparatus and method for identifying devices on a passive type bus such as an ISA bus where peripheral devices do not identify themselves to the host CPU. The apparatus and method of the present invention has particular application to systems where more than one passive (e.g., ISA type) bus may be implemented and a host CPU has no indication as to which bus a device is coupled to. The data lines of the bus are tied through a pull-up circuit to a logical high level voltage (V.sub.CC) such that, for example in a sixteen-bit data bus, the output data is FF hexadecimal. When a read request is generated on the bus, the bus controller detects whether the data on the bus changes from FF hexadecimal. If a change is detected, then the address device is present on that bus. If the addressed device outputs a data value of FF hexadecimal, that data value is passed through as valid data.

Abstract: An apparatus and method for identifying devices on a passive type bus such as an ISA bus where peripheral devices do not identify themselves to the host CPU. The apparatus and method of the present invention has particular application to systems where more than one passive (e.g., ISA type) bus may be implemented and a host CPU has no indication as to which bus a device is coupled to. The data lines of the bus are tied through a pull-up circuit to a logical high level voltage (V.sub.CC) such that, for example in a sixteen-bit data bus, the output data is FF hexadecimal. When a read request is generated on the bus, the bus controller detects whether the data on the bus changes from FF hexadecimal. If a change is detected, then the address device is present on that bus. If the addressed device outputs a data value of FF hexadecimal, that data value is passed through as valid data.