Abstract: Exemplary embodiments provide separate SA system-level functionalities or tasks, which are conventionally performed by a multitude of distinct station-level devices, through a single SA device having a plurality of Processing Units (PU). The latter are either distinct Central Processing Units (CPUs) mounted on the same processor board, or distinct processing cores of a single multi-core CPU sharing the same Random Access Memory (RAM). Virtualization techniques are used in supporting multiple instances of Operating Systems (OS) on the plurality of PUs, to create distinct and mutually isolated execution environments are created. Each of these execution environments hosts a single functionality out of a Supervisory Control And Data Acquisition (SCADA) functionality, a gateway functionality, an engineering workplace functionality, and a firewall functionality.

Abstract: A digital signal processor implementation of three algorithms used to detect high impedance faults. The algorithms can be wavelet based, higher order statistics based and neural network based. The algorithms are modified to process one second of data instead of ten seconds of data and a double buffered acquisition is connected to the output of the algorithms.

Abstract: An apparatus, system, and method for detecting high impedance faults in electrical power lines using a composite high impedance fault detection system having a voter logic that samples the logical outputs from a plurality of independent high impedance detection systems and determines a high impedance fault if any two of the plurality of independent high impedance detection systems indicates a high impedance fault. Preferably, the plurality of high impedance detection systems include a wavelet based high impedance fault detection system having a first logical output, a higher order statistics based high impedance fault detection system having a second logical output, and a neural net based high impedance fault detection system having a third logical output. Preferably, each of the plurality of high impedance fault detection systems includes an independent high impedance fault detection application that independently detects a high impedance fault on the electrical power line.

Abstract: A digital signal processor implementation of three algorithms used to detect high impedance faults. The algorithms can be wavelet based, higher order statistics based and neural network based. The algorithms are modified to process one second of data instead of ten seconds of data and a double buffered acquisition is connected to the output of the algorithms.

Abstract: An apparatus, system, and method for detecting high impedance faults in electrical power lines using a composite high impedance fault detection system having a voter logic that samples the logical outputs from a plurality of independent high impedance detection systems and determines a high impedance fault if any two of the plurality of independent high impedance detection systems indicates a high impedance fault. Preferably, the plurality of high impedance detection systems include a wavelet based high impedance fault detection system having a first logical output, a higher order statistics based high impedance fault detection system having a second logical output, and a neural net based high impedance fault detection system having a third logical output. Preferably, each of the plurality of high impedance fault detection systems includes an independent high impedance fault detection application that independently detects a high impedance fault on the electrical power line.

Abstract: An improved high impedance fault (HIF) detection system comprises an analyzer located at a circuit breaker or substation with feeders, wherein the analyzer analyzes current and/or voltage waveforms to detect a HIF on the feeder or on one of a plurality of laterals coupled to the feeder; a plurality of remote outage detectors located respectively at corresponding customer sites, each remote outage detector including a mechanism to detect a loss of potential or power at the corresponding site; and a computer in communication with the analyzer and the remote outage detectors.

Abstract: Method and apparatus for performing point to point verification of devices in a SCADA system are provided. An intelligent electronic device (IED), having two modes of operation--normal and simulation--provides simulated IED data to a SCADA device on command. The IED is capable of continuing to perform its normal functions of monitoring a process under control during the simulation mode. The IED accepts simulation data either locally through a user interface or from a SCADA device over/through a communication port. The simulation data is then stored in a memory area of the IED. During simulation mode, the IED does not update the memory area but rather provides data from this area to a SCADA device on command.