Abstract: In accordance with embodiments of the present technology, region based selective error detection and correction techniques provide for the tradeoff between the safety of error detection and error correction (EDEC) protection, and the higher bandwidth and capacity of non-EDEC protection for different uses.

Abstract: Embodiments of the claimed subject matter provide systems and methods for protecting data in dynamically allocated regions of memory. The method can include receiving the read request where the read request comprises a virtual address associated with a memory and determining a physical address associated with the virtual address. The further includes determining whether the physical address associated with the virtual address is read protected and determining whether the read request is from a component allowed to access read protected memory. The read protected memory was dynamically allocated on a per page basis. The method further includes in response to determining that the read request is to a read protected physical address and determining that the component is allowed to access read protected memory, sending the data from the physical address in the memory.

Abstract: Embodiments of the claimed subject matter provide systems and methods for protecting data in dynamically allocated regions of memory. The method can include receiving the read request where the read request comprises a virtual address associated with a memory and determining a physical address associated with the virtual address. The further includes determining whether the physical address associated with the virtual address is read protected and determining whether the read request is from a component allowed to access read protected memory. The read protected memory was dynamically allocated on a per page basis. The method further includes in response to determining that the read request is to a read protected physical address and determining that the component is allowed to access read protected memory, sending the data from the physical address in the memory.

Abstract: In a multiple render target mode, a pixel shader computes color values for pixels and stores the computed color values in a register file. The register file acts as a buffer for the computed color values. Conventionally writing pixels in the order they are received (pixel-major order) can result in large strides across memory in the frame buffer. At least a minimum amount of work should be done within a DRAM page, for example, to cover the overhead required in opening the DRAM page. Therefore, color values are written from the register file to two or more targets in a frame buffer in a target-major order within a segment. Writing in a target-major order (sequential with respect to targets but non-sequential with respect to quads received and processed) yields coherent writes to frame buffer memory and improves memory efficiency.

Abstract: One embodiment of the present invention sets forth an architecture for optimizing graphics rendering efficiency by advancing the Z-test operation prior to pixel shading whenever possible. The current rendering state, as maintained by the setup engine, determines whether advancing the Z-test function above the shader engine for “early” Z-testing is possible or whether the Z-test function should be deferred until after shading operations for “late” Z-testing. Data is dynamically routed to each processing engine in the pipeline, so that the appropriate data flow for either early Z or late Z is dynamically constructed, as determined by the current rendering state. Efficiency is gained by relieving the shader engine of unnecessary work whenever possible by discarding pixels before they enter the shader engine. The same functional units are utilized in both early Z and late Z configurations, minimizing any additional hardware required for implementation.

Abstract: A parallel array architecture for a graphics processor includes a multithreaded core array including a plurality of processing clusters, each processing cluster including at least one processing core operable to execute a pixel shader program that generates pixel data from coverage data; a rasterizer configured to generate coverage data for each of a plurality of pixels; and pixel distribution logic configured to deliver the coverage data from the rasterizer to one of the processing clusters in the multithreaded core array. The pixel distribution logic selects one of the processing clusters to which the coverage data for a first pixel is delivered based at least in part on a location of the first pixel within an image area. The processing clusters can be mapped directly to the frame buffers partitions without a crossbar so that pixel data is delivered directly from the processing cluster to the appropriate frame buffer partitions.

Abstract: A power strip having a plurality of grounded outlet receptacles includes a motion sensor circuit. The motion sensor circuit controls operation of the power strip, and hence, operation of all electronic components plugged into the power strip.

Abstract: This disclosure is directed to a method and combined apparatus for converting or translating the immense potential energy of the deep sea water into useful work by providing a jointly enclosed environment in a column or mass of a fluid in which a container or vessel is maintained under a pressure which is less than that of the pressure exerted by the deep sea water. The apparatus consists of two, in all respects entirely independent, machines with individual performances and with entirely separated energy consumptions operatively connected to achieve the end result.A fluid activated work producing machine is disposed so as to be actuated by the continuous differential in pressure between the pressure exerted by the continuous deep sea water and the low pressure of the environment in an associated container or vessel.