Patents by Inventor Steven Avanzino

Steven Avanzino has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5646448
    Abstract: A multilayer semiconductor structure includes a conductive via. The conductive via includes a pellet of metal having a high resistance to electromigration. The pellet is made from a conformal layer of copper or gold deposited over the via to form a copper or gold reservoir or contact located in the via. A barrier layer is provided between the reservoir and an insulating layer to prevent the pellet from diffusing into the insulating layer. The pellet can be formed by selective deposition or by etching a conformal layer. The conformal layer can be deposited by sputtering, collimated sputtering, chemical vapor deposition (CVD), dipping, evaporating, or by other means. The barrier layer and pellet may be etched by anisotropic dry etching, plasma-assisted etching, or other layer removal techniques.
    Type: Grant
    Filed: August 19, 1996
    Date of Patent: July 8, 1997
    Assignee: Advanced Micro Devices
    Inventors: Richard K. Klein, Darrell Erb, Steven Avanzino, Robin Cheung, Scott Luning, Bryan Tracy, Subhash Gupta, Ming-Ren Lin
  • Patent number: 5639691
    Abstract: A multilayer semiconductor structure includes a conductive via. The conductive via includes a pellet of metal having a high resistance to electromigration. The pellet is made from a conformal layer of copper or gold deposited over the via to form a copper or gold reservoir or contact located in the via. A barrier layer is provided between the reservoir and an insulating layer to prevent the pellet from diffusing into the insulating layer. The pellet can be formed by selective deposition or by etching a conformal layer. The conformal layer can be deposited by sputtering, collimated sputtering, chemical vapor deposition (CVD), dipping, evaporating, or by other means. The barrier layer and pellet may be etched by anisotropic dry etching, plasma-assisted etching, or other layer removal techniques.
    Type: Grant
    Filed: January 24, 1996
    Date of Patent: June 17, 1997
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Richard K. Klein, Darrell M. Erb, Steven Avanzino, Robin Cheung, Scott Luning, Bryan Tracy, Subhash Gupta, Ming-Ren Lin
  • Patent number: 5614765
    Abstract: An interconnection level of conductive lines and connecting vias separated by insulation for integrated circuits and substrate carriers for semiconductor devices using dual damascene with only one mask pattern for the formation of both the conductive lines and vias. The mask pattern of conductive lines contains laterally enlarged areas where the via openings are to formed in the insulating material. After the conductive line openings with laterally enlarged areas are created, the openings are filled with a conformal material whose etch selectivity is substantially less than the etch selectivity of the insulating material to the enchant for etching the insulating material and whose etch selectivity is substantially greater than the insulating material to its enchant. The conformal material is anisotropically etched to form sidewalls in the enlarged area and remove the material between the sidewalls but leave material remaining in the parts of the conductive lines openings.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: March 25, 1997
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Steven Avanzino, Subhash Gupta, Rich Klein, Scott D. Luning, Ming-Ren Lin