Abstract: Multiple channels of a multi-channel analyzer are allocated among multiple users such that each user can initiate and retrieve the results of separate diagnostic sessions or strategies. Each analyzer channel includes an input connection port, a trace buffer memory and logic circuitry. The input connection port is operably connected to a unique node in the communication network. A host processor assigns ownership of a unique set of analyzer channels to at least two users such that each user can initiate separate simultaneously established traces on the communication network. The logic circuitry monitors frame data on the connection port at each node in accordance with a set of instructions established by the user assigned to the analyzer channel for that node, and the traces are captured in response to the set of instructions such that each user retrieves only results of the analyzer channels assigned to that user.

Abstract: Multiple channels of a multi-channel analyzer are allocated among multiple users such that each user can initiate and retrieve the results of separate diagnostic sessions or strategies. Each analyzer channel of the multi-channel analyzer includes an input connection port, a trace buffer memory and logic circuitry. The input connection port of each analyzer channel is operably connected to a unique node in the communication network. A host processor connected to each analyzer channel assigns ownership of a unique set of analyzer channels to at least two different users such that each user can initiate separate traces that are simultaneously established on the communication network.

Abstract: Multiple channels of a multi-channel analyzer are allocated among multiple users such that each user can initiate and retrieve the results of separate diagnostic sessions. Each analyzer channel includes an input connection port, a trace buffer memory and logic circuitry. Each input connection port is operably connected to a unique node in the communication network. A host processor connected to each analyzer channel assigns ownership of a unique set of analyzer channel to at least two different users such that each user can initiate separate traces that are simultaneously established on the connection port at each node in accordance with a set of instructions established by the user assigned to the analyzer channel for that node, and the traces are captured in response to the set of instructions for each analyzer channel such that each user retrieves only the results of the analyzer channels assigned to that user.

Abstract: An integrated multi-channel Fiber Channel analyzer provides coordinated and cooperative triggering and capture of data across multiple channels in a Fiber Channel network. The integrated multi-channel analyzer accommodates up to sixteen separate analyzer channels in a single cabinet. Each analyzer channel is comprised of an input port connection to the Fiber Channel network, a trace buffer memory that captures data and logic circuitry that controls the operation of the trace buffer memory in response to a status condition. A high speed status bus is connected to each analyzer channel and propagates the status conditions of each analyzer channel to all other analyzer channels. In this way, the integrated multi-channel analyzer allows for distributive control over triggering decisions across multiple analyzer channels, and also allows for multi-level triggering where different conditions may be detected by different analyzer channels.

Abstract: Multiple channels of a multi-channel analyzer are allocated among multiple users such that each user can initiate and retrieve the results of separate diagnostic sessions or strategies. Each analyzer channel of the multi-channel analyzer includes an input connection port, a trace buffer memory and logic circuitry. The input connection port of each analyzer channel is operably connected to a unique node in the communication network. A host processor connected to each analyzer channel assigns ownership of a unique set of analyzer channels to at least two different users such that each user can initiate separate traces that are simultaneously established on the communication network.

Abstract: A deep trace buffer management system for a protocol analyzer includes a hardware search engine that locates specified data patterns within the trace buffer as directed by a host processor. The protocol analyzer is preferably connected to a laptop computer that serves as the host processor, and the protocol analyzer preferably is housed in a portable chassis separate from the host processor and has a host port to connect to the host processor through a relatively small bandwidth port. An interface port connects the protocol analyzer to the communication interface under analysis. Logic circuitry controls selective read and write operations of traces to and from the trace buffer in response to parameters as directed by the host processor.

Abstract: A deep trace buffer management system for a protocol analyzer includes a hardware search engine that locates specified data patterns within the trace buffer as directed by a host processor. The protocol analyzer is preferably connected to a laptop computer that serves as the host processor, and the protocol analyzer preferably is housed in a portable chassis separate from the host processor and has a host port to connect to the host processor through a relatively small bandwidth port. An interface port connects the protocol analyzer to the communication interface under analysis. Logic circuitry controls selective read and write operations of traces to and from the trace buffer in response to parameters as directed by the host processor.

Abstract: A deep trace buffer management system for a protocol analyzer includes a hardware search engine that locates specified data patterns within the trace buffer as directed by a host processor. The protocol analyzer is preferably connected to a laptop computer that serves as the host processor, and the protocol analyzer preferably is housed in a portable chassis separate from the host processor and has a host port to connect to the host processor through a relatively small bandwidth port. An interface port connects the protocol analyzer to the communication interface under analysis. Logic circuitry controls selective read and write operations of traces to and from the trace buffer in response to parameters as directed by the host processor.

Abstract: A universal electrical interface system connects to a small computer system interface (SCSI) bus. In a passive embodiment, a set of single-ended receivers and a set of differential receivers receive electrical signals on the SCSI bus according to the single-ended or differential protocol, respectively, when each set of receivers is enabled. In an active embodiment, a set of single-ended transceivers and a set of differential transceivers transmit and receive electrical signals on the SCSI bus according to the single-ended or differential protocol, respectively, when each set of transceivers is enabled. A control mechanism connected to both sets of receivers or transceivers automatically determines whether the SCSI bus is configured to use either the single-ended or differential parallel interface protocol and selectively enables the set of single ended receivers or transceivers, or the set of differential receivers or transceivers.

Abstract: A universal electrical interface system connects to a small computer system interface (SCSI) bus. In a passive embodiment, a set of single-ended receivers and a set of differential receivers receive electrical signals on the SCSI bus according to the single-ended or differential protocol, respectively, when each set of receivers is enabled. In an active embodiment, a set of single-ended transceivers and a set of differential transceivers transmit and receive electrical signals on the SCSI bus according to the single-ended or differential protocol, respectively, when each set of transceivers is enabled. A control mechanism connected to both sets of receivers or transceivers automatically determines whether the SCSI bus is configured to use either the single-ended or differential parallel interface protocol and selectively enables the set of single ended receivers or transceivers, or the set of differential receivers or transceivers.

Abstract: A software architecture and method for controlling multi-thread peripheral operations in an initiator device such as a computer equipped with a SCSI interface. A data structure is provided for storage of thread context parameters. High level code places a low level driver in either a single-thread or multi-thread mode, and then issues peripheral commands by calling the low level driver. The low level driver manages the interface protocol, returning to the high level code when a command is complete, or if in multi-thread mode, when a command disconnects. Management of the data structure is accomplished by the low level driver, minimizing the impact of multi-thread operations on the high level code.