Patents by Inventor Steven C. Bird
Steven C. Bird has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11057984Abstract: A circuit includes a printed circuit board including a first portion defining a window formed as a first void on a first side of the printed circuit board and a second portion defining a cavity formed as a second void opposite the first void on a second side of the printed circuit board. The circuit further includes a heat sink inserted in the second void, the heat sink having a first side forming a bottom of the first void and the bottom of the first void within the printed circuit board. The circuit yet further includes at least one electronic circuit die mounted to the first side of the heat sink and electrically coupled to the first side of the printed circuit board.Type: GrantFiled: November 26, 2018Date of Patent: July 6, 2021Assignee: II-VI DELAWARE, INC.Inventors: Steven C. Bird, Henry Meyer Daghighian
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Patent number: 10667388Abstract: An optical waveguide is disclosed. In a disclosed embodiment, the optical waveguide includes a first aluminum nitride (AlN) thin film disposed on a layer of high-frequency polymer. A second AlN thin film is embedded in the first AlN thin film. In disclosed embodiments, the nitrogen concentration level of the first AlN thin film is different than the concentration level of the second AlN thin film.Type: GrantFiled: November 4, 2019Date of Patent: May 26, 2020Assignee: II-VI Delaware Inc.Inventors: Henry Meyer Daghighian, Steven C. Bird
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Publication number: 20200068706Abstract: An optical waveguide is disclosed. In a disclosed embodiment, the optical waveguide includes a first aluminum nitride (AlN) thin film disposed on a layer of high-frequency polymer. A second AlN thin film is embedded in the first AlN thin film. In disclosed embodiments, the nitrogen concentration level of the first AlN thin film is different than the concentration level of the second AlN thin film.Type: ApplicationFiled: November 4, 2019Publication date: February 27, 2020Inventors: Henry Meyer Daghighian, Steven C. Bird
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Patent number: 10470302Abstract: A printed circuit board may include an aluminum nitride (AIN) substrate that includes an AIN thin film and a layer of high-frequency polymer as a carrier substrate of the AIN thin film. The AIN substrate forms a first layer of the printed circuit board. The AIN substrate comprises a heat spreader that laterally spreads out heat from a heat sink on the printed circuit board to form a thermal dissipation path parallel with a signal path on the printed circuit board. The printed circuit board may include a main substrate aligned to and bonded with the AIN substrate. The main substrate may include one or more additional layers of the printed circuit board.Type: GrantFiled: April 25, 2016Date of Patent: November 5, 2019Assignee: Finisar CorporationInventors: Henry Meyer Daghighian, Steven C. Bird
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Publication number: 20190166684Abstract: A circuit includes a printed circuit board including a first portion defining a window formed as a first void on a first side of the printed circuit board and a second portion defining a cavity formed as a second void opposite the first void on a second side of the printed circuit board. The circuit further includes a heat sink inserted in the second void, the heat sink having a first side forming a bottom of the first void and the bottom of the first void within the printed circuit board. The circuit yet further includes at least one electronic circuit die mounted to the first side of the heat sink and electrically coupled to the first side of the printed circuit board.Type: ApplicationFiled: November 26, 2018Publication date: May 30, 2019Inventors: Steven C. Bird, Henry Meyer Daghighian
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Publication number: 20190164891Abstract: A circuit of tunable differential vias may include a first tunable via circuit configured to couple a first signal of a differential signal pair from a first outer surface of a printed circuit board (PCB) to a second outer surface of the PCB. The circuit may further include a second tunable via circuit configured to couple a second signal of the differential signal pair from the first outer surface of the PCB to the second outer surface of the PCB. The first tunable via circuit may further include a first buried via spatially offset from the second tunable via circuit to cause a predetermined impedance for the first and second signals through the first and second tunable via circuits at an operating frequency.Type: ApplicationFiled: November 27, 2017Publication date: May 30, 2019Inventors: Steven C. Bird, Ron Greenlaw, Henry Meyer Daghighian
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Patent number: 10111343Abstract: Some embodiments relate to micro vias in printed circuit boards (PCBs). In an example, a PCB may include a PCB substrate and a micro via. The micro via may extend between opposing surfaces of the PCB substrate and may have a diameter less than or equal to about 100 microns. In another example, a method of forming micro vias in a PCB may include forming a through hole in a PCB substrate of the PCB. The method may also include positioning a pillar that is electrically conductive within the through hole. The method may also include backfilling the through hole around the pillar with an epoxy backfill.Type: GrantFiled: November 11, 2014Date of Patent: October 23, 2018Assignee: FINISAR CORPORATIONInventors: Henry Meyer Daghighian, Steven C. Bird, YongShan Zhang
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Patent number: 9526185Abstract: A hybrid printed circuit board may include a top layer, a bottom layer, and a plurality of internal layers stacked up between the top layer and the bottom layer. The plurality of internal layers may include a first internal layer below the top layer and a second internal layer above the bottom layer. The hybrid printed circuit board may include first unreinforced laminate placed between the top layer and the first internal layer. The hybrid circuit board may additionally include second unreinforced laminate placed between the second internal layer and the bottom layer. The hybrid printed circuit board may include third laminate placed between adjacent internal layers of the plurality of internal layers.Type: GrantFiled: April 8, 2014Date of Patent: December 20, 2016Assignee: FINISAR CORPORATIONInventors: Henry Meyer Daghighian, Steven C. Bird, Gerald Douglas Babel
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Publication number: 20160323992Abstract: A printed circuit board may include an aluminum nitride (AIN) substrate that includes an AIN thin film and a layer of high-frequency polymer as a carrier substrate of the AIN thin film. The AIN substrate forms a first layer of the printed circuit board. The AIN substrate comprises a heat spreader that laterally spreads out heat from a heat sink on the printed circuit board to form a thermal dissipation path parallel with a signal path on the printed circuit board. The printed circuit board may include a main substrate aligned to and bonded with the AIN substrate. The main substrate may include one or more additional layers of the printed circuit board.Type: ApplicationFiled: April 25, 2016Publication date: November 3, 2016Inventors: Henry Meyer Daghighian, Steven C. Bird
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Patent number: 9326373Abstract: A printed circuit board may include an aluminum nitride (AIN) substrate that includes an AIN thin film and a layer of high-frequency polymer as a carrier substrate of the AIN thin film. The AIN substrate forms a first layer of the printed circuit board. The AIN substrate comprises a heat spreader that laterally spreads out heat from a heat sink on the printed circuit board to form a thermal dissipation path parallel with a signal path on the printed circuit board. The printed circuit board may include a main substrate aligned to and bonded with the AIN substrate. The main substrate may include one or more additional layers of the printed circuit board.Type: GrantFiled: April 7, 2015Date of Patent: April 26, 2016Assignee: FINISAR CORPORATIONInventors: Henry Meyer Daghighian, Steven C. Bird
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Publication number: 20150296610Abstract: A printed circuit board may include an aluminum nitride (AlN) substrate that includes an AlN thin film and a layer of high-frequency polymer as a carrier substrate of the AlN thin film. The AlN substrate forms a first layer of the printed circuit board. The AlN substrate comprises a heat spreader that laterally spreads out heat from a heat sink on the printed circuit board to form a thermal dissipation path parallel with a signal path on the printed circuit board. The printed circuit board may include a main substrate aligned to and bonded with the AlN substrate. The main substrate may include one or more additional layers of the printed circuit board.Type: ApplicationFiled: April 7, 2015Publication date: October 15, 2015Inventors: Henry Meyer Daghighian, Steven C. Bird
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Publication number: 20150289368Abstract: A hybrid printed circuit board is described. The hybrid printed circuit board may include a top layer, a bottom layer, and a plurality of internal layers stacked up between the top layer and the bottom layer. The plurality of internal layers may include a first internal layer below the top layer and a second internal layer above the bottom layer. The hybrid printed circuit board may include first unreinforced laminate placed between the top layer and the first internal layer. The hybrid circuit board may additionally include second unreinforced laminate placed between the second internal layer and the bottom layer. The hybrid printed circuit board may include third laminate placed between adjacent internal layers of the plurality of internal layers.Type: ApplicationFiled: April 8, 2014Publication date: October 8, 2015Applicant: FINISAR CORPORATIONInventors: Henry Meyer Daghighian, Steven C. Bird, Gerald Douglas Babel
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Publication number: 20150136468Abstract: Some embodiments relate to micro vias in printed circuit boards (PCBs). In an example, a PCB may include a PCB substrate and a micro via. The micro via may extend between opposing surfaces of the PCB substrate and may have a diameter less than or equal to about 100 microns. In another example, a method of forming micro vias in a PCB may include forming a through hole in a PCB substrate of the PCB. The method may also include positioning a pillar that is electrically conductive within the through hole. The method may also include backfilling the through hole around the pillar with an epoxy backfill.Type: ApplicationFiled: November 11, 2014Publication date: May 21, 2015Inventors: Henry Meyer Daghighian, Steven C. Bird, YongShan Zhang
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Patent number: 8990754Abstract: Techniques for optimizing application specific integrated circuit (ASIC) and other IC pin assignment corresponding to a high density interconnect (HDI) printed circuit board (PCB) layout are provided. Applying the techniques described herein, pin assignments may be systematically and strategically planned, for example, in an effort to reduce the PCB layer count and associated cost, increase signal integrity and speed, reduce the surface area used by an ASIC and its support circuitry, reduce plane perforations, and reduce via crosstalk when compared to conventional designs with an ASIC mounted on a multilayered PCB.Type: GrantFiled: July 12, 2010Date of Patent: March 24, 2015Assignee: Cisco Technology, Inc.Inventors: Steven C. Bird, Linda M. Mazaheri, Bob Needham, Phuong Rosalynn Duong
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Patent number: 8344266Abstract: Techniques for optimizing application specific integrated circuit (ASIC) and other IC pin assignment corresponding to a high density interconnect (HDI) printed circuit board (PCB) layout are provided. Applying the techniques described herein, pin assignments may be systematically and strategically planned, for example, in an effort to reduce the PCB layer count and associated cost, increase signal integrity and speed, reduce the surface area used by an ASIC and its support circuitry, reduce plane perforations, and reduce via crosstalk when compared to conventional designs with an ASIC mounted on a multilayered PCB.Type: GrantFiled: August 10, 2007Date of Patent: January 1, 2013Assignee: Cisco Technology, Inc.Inventors: Steven C. Bird, Linda M. Mazaheri, Bob Needham, Phuong Rosalynn Duong
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Patent number: 7979983Abstract: Techniques for optimizing application specific integrated circuit (ASIC) and other IC pin assignment corresponding to a high density interconnect (HDI) printed circuit board (PCB) layout are provided. Applying the techniques described herein, pin assignments may be systematically and strategically planned, for example, in an effort to reduce the PCB layer count and associated cost, increase signal integrity and speed, reduce the surface area used by an ASIC and its support circuitry, reduce plane perforations, and reduce via crosstalk when compared to conventional designs with an ASIC mounted on a multilayered PCB.Type: GrantFiled: April 4, 2007Date of Patent: July 19, 2011Assignee: Cisco Technology, Inc.Inventors: Steven C. Bird, Linda M. Mazaheri, Bob Needham, Phuong Rosalynn Duong
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Publication number: 20100270681Abstract: Techniques for optimizing application specific integrated circuit (ASIC) and other IC pin assignment corresponding to a high density interconnect (HDI) printed circuit board (PCB) layout are provided. Applying the techniques described herein, pin assignments may be systematically and strategically planned, for example, in an effort to reduce the PCB layer count and associated cost, increase signal integrity and speed, reduce the surface area used by an ASIC and its support circuitry, reduce plane perforations, and reduce via crosstalk when compared to conventional designs with an ASIC mounted on a multilayered PCB.Type: ApplicationFiled: July 12, 2010Publication date: October 28, 2010Inventors: Steven C. Bird, Linda M. Mazaheri, Bob Needham, Phuong Rosalynn Duong
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Patent number: 7797663Abstract: Methods and apparatus for accessing a high speed signal routed on a conductive trace on an internal layer of a printed circuit board (PCB) using high density interconnect (HDI technology) are provided. The conductive trace may be coupled to a microvia (?Via) having a conductive dome disposed above the outer layer pad of the ?Via. In-circuit test (ICT) fixtures or high speed test probes may interface with the conductive dome to test the high speed signal with decreased reflection loss and other parasitic effects when compared to conventional test points utilizing plated through-hole (PTH) technology.Type: GrantFiled: April 4, 2007Date of Patent: September 14, 2010Assignee: Cisco Technology, Inc.Inventors: Steven C. Bird, Varoujan Malian, Mudasir Ahmad, Charles H. Casale, Danlu Tang
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Patent number: 7757196Abstract: Techniques for optimizing application specific integrated circuit (ASIC) and other IC pin assignment corresponding to a high density interconnect (HDI) printed circuit board (PCB) layout are provided. Applying the techniques described herein, pin assignments may be systematically and strategically planned, for example, in an effort to reduce the PCB layer count and associated cost, increase signal integrity and speed, reduce the surface area used by an ASIC and its support circuitry, reduce plane perforations, and reduce via crosstalk when compared to conventional designs with an ASIC mounted on a multilayered PCB.Type: GrantFiled: April 4, 2007Date of Patent: July 13, 2010Assignee: Cisco Technology, Inc.Inventors: Steven C. Bird, Linda M. Mazaheri, Bob Needham, Phuong Rosalynn Duong
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Publication number: 20080250377Abstract: Methods and apparatus for accessing a high speed signal routed on a conductive trace on an internal layer of a printed circuit board (PCB) using high density interconnect (HDI technology) are provided. The conductive trace may be coupled to a microvia (?Via) having a conductive dome disposed above the outer layer pad of the ?Via. In-circuit test (ICT) fixtures or high speed test probes may interface with the conductive dome to test the high speed signal with decreased reflection loss and other parasitic effects when compared to conventional test points utilizing plated through-hole (PTH) technology.Type: ApplicationFiled: April 4, 2007Publication date: October 9, 2008Inventors: Steven C. Bird, Varoujan Malian, Mudasir Ahmad, Charles H. Casale, Danlu Tang