Abstract: A photovoltaic generator constructed on an SOI N− layer subdivided into a series of connected isolated tubs whereby the isolated tubs are subdivided by a matrix of trenched wells. A P+ junction is formed into the top surface of each well to define a photovoltaic generator junction for its respective well.

Abstract: A photo voltaic generator constructed on an SOI N− layer subdivided into a series of connected isolated tubs whereby the isolated tubs are subdivided by a matrix of trenched wells. A P+ junction is formed into the top surface of each well to define a photo voltaic generator junction for its respective well.

Abstract: N+ or P+ diffusions are formed in a lightly doped P type or N type starting wafer. Individual planar and spaced cells or tubs are then formed by etching an array of intersecting trenches between the P+ (or N+) diffusions. The trenches extend through the thin device layer to a predefined depth and are filled with a dielectric and with polysilicon to dielectrically insulate each of the tubs. At least one diffusion of each cell is connected to a diffusion of an adjacent cell to connect each of a predetermined number of the cells. The N+ or (P+) diffusions may be each enclosed by a ring shaped P+ or N+ contact diffusion. An MOS-gated device may be integrated into the same chip and may be a lateral or vertical MOSFET or a lateral or vertical IGBT.

Abstract: N+ or P+ diffusions are formed in a lightly doped P type or N type starting wafer. Individual planar and spaced cells or tubs are then formed by etching an array of intersecting trenches between the P+ (or N+) diffusions. The trenches extend through the thin device layer to a predefined depth and are filled with a dielectric and with polysilicon to dielectrically insulate each of the tubs. At least one diffusion of each cell is connected to a diffusion of an adjacent cell to connect each of a predetermined number of the cells. The N+ or (P+) diffusions may be each enclosed by a ring shaped P+ or N+ contact diffusion. An MOS-gated device may be integrated into the same chip and may be a lateral or vertical MOSFET or a lateral or vertical IGBT.

Abstract: A process for etching and filling a trench prevents the top opening of the trench from being closed off prior to the trench being completely filled. After a masking layer is deposited and patterned, the trench is etched and then the masking layer is removed. A first liner insulating layer is grown or deposited and is then etched anisotropically to remove the layer from the top surface of the substrate as well as from the top portion of the walls of the trench. A second, thinner liner layer is grown or deposited on the exposed portion of the walls of the trench to provide surface and edge protection. A polysilicon layer is then deposited to fill the trench and is planarized to remove the portion deposited on the top surface of the substrate. Alternatively, the thinner oxide liner can be omitted, and the polysilicon is removed by chemical mechanical polishing until the trench liner oxide appears on the top surface. An overlaying insulation layer is then deposited.

Abstract: A process for etching and filling a trench prevents the top opening of the trench from being closed off prior to the trench being completely filled. After a masking layer is deposited and patterned, the trench is etched and then the masking layer is removed. A first liner insulating layer is grown or deposited and is then etched anisotropically to remove the layer from the top surface of the substrate as well as from the top portion of the walls of the trench. A second, thinner liner layer is grown or deposited on the exposed portion of the walls of the trench to provide surface and edge protection. A polysilicon layer is then deposited to fill the trench and is planarized to remove the portion deposited on the top surface of the substrate. Alternatively, the thinner oxide liner can be omitted, and the polysilicon is removed by chemical mechanical polishing until the trench liner oxide appears on the top surface. An overlaying insulation layer is then deposited.

Abstract: A photovoltaic generator device for producing an output sufficient to turn on a MOS-gated device consists of a plurality of planar photogenerator cells connected in series. Each of the photovoltaic generator cells is contained on its own respective insulated tub. The insulated tubs are formed by wafer bonding a device wafer to a handle wafer with a dielectric isolation layer between them. Prior to joining the two wafers, a reflective layer is deposited on the surface of the device wafer to maximize absorption of incident light by the photogenerator cell. The individual tubs are isolated by trenches which enclose each tub and which extend through the reflective and to the dielectric layers between the device and handle wafers. Each tub is formed of an N.sup.- body having a shallow P.sup.+ diffusion. N.sup.+ contact regions are formed in the N.sup.- body and contact strips connect the devices of each of the tubs in series by connecting the P.sup.+ diffusions of one tub to the N.sup.+ contact of an adjacent tub.