Abstract: An area array interconnect device (such as of the TAB type) has a plurality of input/output (I/O) leads for connection to an electronic device such as an IC. The interconnect device also has arrays of lead lines in areas remote from the I/O leads, e.g., central or internal areas, which are connected by vias to ground and/or power pads on corresponding areas of the electronic device.

Abstract: A circuit board electrical interconnection system, including improved, elongated, bodily-rotatable interconnect elements, is disclosed. Each element has tab portions projection angularly from the opposing ends of the element, which tab portions define a pair of pad engagement surfaces. The pad engagement surfaces engage corresponding contact pads on opposing surfaces of two circuit boards by means of elastic support member. The element is divided longitudinally, axially or laterally into a plurality of sectors. Some sectors are electrically conductive, while others have other electrically predetermined characteristics. The two types of sectors are arranged in an alternating patter. The non-conducting sectors may be comprised of insulative, resistive or capacitive materials.

Abstract: An interconnect device for electronic components, such as integrated circuits, multichip modules and the like, and the method of manufacture thereof are presented. The interconnect device has at least three layers of circuitry, one for signal transmission and two for voltage planes (power and ground). The interconnect device is made by a processing on a stainless steel carrier plate to achieve high lead count capability with fine line widths and spacing, as well as precise registration layer to layer. Laser drilling is used to define interconnect vias between signal and voltage (power and ground) plane layers.

Abstract: An interconnect device for electronic components, such as integrated circuits, multichip modules and the like, and the method of manufacture thereof are presented. The interconnect device has at least three layers of circuitry, one for signal transmission and two for voltage planes (power and ground). The interconnect device is made by a processing on a stainless steel carrier plate to achieve high lead count capability with fine line widths and spacing, as well as precise registration layer to layer. Laser drilling is used to define interconnect vias between signal and voltage (power and ground) plane layers.

Abstract: High frequency noise is decoupled from power supplied to a Pin Grid Array (PGA) package by insertion of a decoupling capacitor between the PGA package and printed circuit board. The decoupling capacitor comprises a dielectric material sandwiched between a pair of conductors and having a plurality of leads extending from each conductor. In accordance with the present invention, the decoupling capacitor is individually dimensioned and configured to fit under a PGA package and correspond to the power and ground pin configuration of that PGA package.