Abstract: Techniques disclosed herein relate to determining a calibrated measurement value indicative of a physiological condition of a patient using sensor calibration data and a performance model. In some embodiments, the techniques involve obtaining one or more electrical signals from a sensing element of a sensing arrangement, where the one or more electrical signals are influenced by a physiological condition in a body of a patient. The techniques also involve obtaining calibration data associated with the sensing element from a data storage element of the sensing arrangement, converting the one or more electrical signals into one or more calibrated measurement parameters using the calibration data, obtaining a performance model associated with the sensing element, obtaining personal data associated with the patient, and determining, using the performance model and based on the personal data and the one or more calibrated measurement parameters, a calibrated output value indicative of the physiological condition.

Abstract: Embodiments of a memory are disclosed that may allow for a negative boost of data lines during a write. The memory device may include a data input circuit, an address decode circuit and a plurality of sub-arrays. Each of the sub-arrays may include a plurality of columns, a write selection circuit, a first write driver circuit, a second write driver circuit, and a boost circuit. Each of the columns may include a plurality of data storage cells. The write selection circuit may select a column of the plurality of columns. Each of the write driver circuits may be configured to discharge a data line of a selected column into a common node. The boost circuit may be configured to initialize the common node to the first voltage level and couple the common node to a second voltage level, where the second voltage level is lower than the first voltage level.

Abstract: Embodiments of a memory are disclosed that may allow for a negative boost of data lines during a write. The memory device may include a data input circuit, an address decode circuit and a plurality of sub-arrays. Each of the sub-arrays may include a plurality of columns, a write selection circuit, a first write driver circuit, a second write driver circuit, and a boost circuit. Each of the columns may include a plurality of data storage cells. The write selection circuit may select a column of the plurality of columns. Each of the write driver circuits may configured to discharge a data line of a selected column into a common node. The boost circuit may be configured to initialize the common node to the first voltage level and couple the common node to a second voltage level, where the second voltage level is lower than the first voltage level.

Abstract: A memory column redundancy mechanism includes a memory having a number of data output ports each configured to output one data bit of a data element. The memory also includes a number of memory columns each connected to a corresponding respective data port. Each memory column includes a plurality of bit cells that are coupled to a corresponding sense amplifier that may differentially output a respective data bit from the plurality of bit cells on an output signal and a complemented output signal. The memory further includes an output selection unit that may select as the output data bit for a given data output port, one of the output signal of the sense amplifier associated with the given data output port or the complemented output signal of the sense amplifier associated with an adjacent data output port dependent upon a respective shift signal for each memory column.

Abstract: Controllable arrays in a memory may be activated and deactivated independently. In one embodiment, a processor may include a memory. The memory may be a de-interleaved memory with independently selectable arrays. Based on an address bit of an address used to access data from the memory, a wordline and downstream components may be activated while another wordline and downstream components may be deactivated.

Abstract: Sense amplifiers in a memory may be activated and deactivated. In one embodiment, a processor may include a memory. The memory may include a number of sense amplifiers. Based on a late arriving address bit of an address used to access data from the memory, a sense amplifier may be activated while another sense amplifier may be deactivated.

Abstract: A dual port memory includes a mechanism for preventing collisions. The memory includes dual port bit cells arranged in rows and columns and each bit cell stores a data bit. The memory also includes a wordline unit that may provide a respective write wordline signal and a respective read wordline signal to each row of bit cells. The wordline unit may also selectively inhibit the read wordline signal for a given row based upon address information that is indicative of whether a write operation will be performed to the given row.

Abstract: A dual port memory includes a mechanism for preventing collisions. The memory includes dual port bit cells arranged in rows and columns and each bit cell stores a data bit. The memory also includes a wordline unit that may provide a respective write wordline signal and a respective read wordline signal to each row of bit cells. The wordline unit may also selectively inhibit the read wordline signal for a given row based upon address information that is indicative of whether a write operation will be performed to the given row.

Abstract: A memory column redundancy mechanism includes a memory having a number of data output ports each configured to output one data bit of a data element. The memory also includes a number of memory columns each connected to a corresponding respective data port. Each memory column includes a plurality of bit cells that are coupled to a corresponding sense amplifier that may differentially output a respective data bit from the plurality of bit cells on an output signal and a complemented output signal. The memory further includes an output selection unit that may select as the output data bit for a given data output port, one of the output signal of the sense amplifier associated with the given data output port or the complemented output signal of the sense amplifier associated with an adjacent data output port dependent upon a respective shift signal for each memory column.

Abstract: Controllable arrays in a memory may be activated and deactivated independently. In one embodiment, a processor may include a memory. The memory may be a de-interleaved memory with independently selectable arrays. Based on an address bit of an address used to access data from the memory, a wordline and downstream components may be activated while another wordline and downstream components may be deactivated.

Abstract: Sense amplifiers in a memory may be activated and deactivated. In one embodiment, a processor may include a memory. The memory may include a number of sense amplifiers. Based on a late arriving address bit of an address used to access data from the memory, a sense amplifier may be activated while another sense amplifier may be deactivated.

Abstract: A sense amplifier (40) uses a body shorting device (60) to selectively electrically short circuit the bodies of two transistors (44, 48) that function as a differential sensing pair. Equalization of charge injected into the bodies functions to minimize offset voltage between the two bodies. The body shorting device selectively shorts the bodies in response to a body control signal after a sense operation and after asserting a precharging signal to initiate precharging of the sense amplifier's outputs.

Abstract: A sense amplifier (40) uses a body shorting device (60) to selectively electrically short circuit the bodies of two transistors (44, 48) that function as a differential sensing pair. Equalization of charge injected into the bodies functions to minimize offset voltage between the two bodies. The body shorting device selectively shorts the bodies in response to a body control signal after a sense operation and after asserting a precharging signal to initiate precharging of the sense amplifier's outputs.

Abstract: A system provides a method and apparatus for accessing information in a cache in a data processing system. The system optimizes a speed-critical path within the cache system by using a prediction scheme. The prediction scheme subdivides the address range of address bits and compares the portions separately. A comparison of a critical portion of the address, along with a prediction bit, are used to generate a prediction.

Abstract: A clock signal (202) is received, wherein the rising edge of the clock signal (202) controls an operation of a memory cell (224) of a memory circuit (200). Address information (204) is received and predecoded prior to the rising edge of the clock signal (202) to produce a row select signal (210). A control signal (201), which is received prior to the rising edge of the clock signal, determines whether the operation is a read operation or a write operation. If the operation is a write operation, new data information (218) is received a data delay after the rising edge of the clock signal (202); the row select signal (210) is delayed such that the memory cell (224) is selected at least a data delay after the rising edge of the clock signal (202); and the new data information (218) is written to the memory cell (224).

Abstract: A selection circuit for a bipolar ECL memory having memory cell connected to cell selection lines and, more particularly, to upper and lower wordlines. The circuit includes a line driver connected to the upper wordline, an input stage for controlling the line driver to activate the upper wordline connected thereto in response to an address signal, and a switching device responsive to the input stage for applying a discharging current to the lower word line to speed up deactivation of the memory cell in response to a change in the address signal. In one embodiment, the line driver is also turned on at an increased rate for a limited time following application of the address signal to speed up the activation of the line.

Abstract: Series terminated ECL buffer circuit and method with an opptimized, temperature compensated output voltage swing. The circuit has a pair of node points and an output transistor configured as an emitter follower, with the base of the transistor connected to one of the node points. Resistors having different values of resistance are connected between a voltage source point and respective ones of the node points, and a temperature compensation network comprising a pair of unilaterally conductive legs of opposite polarity and different resistance values is connected between the node points. A current sink is connected selectively to the node points in response to an input signal to cause current to flow selectively through the resistors and the legs of the compensation network to provide an output voltage swing which is relatively independent of temperature and is centered within a predetermined range such as that specified by the standard "ECL100K" specification.