Patents by Inventor Steven C. Woo
Steven C. Woo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9263103Abstract: A system that calibrates timing relationships between signals involved in performing write operations is described. This system includes a memory controller which is coupled to a set of memory chips, wherein each memory chip includes a phase detector configured to calibrate a phase relationship between a data-strobe signal and a clock signal received at the memory chip from the memory controller during a write operation. Furthermore, the memory controller is configured to perform one or more write-read-validate operations to calibrate a clock-cycle relationship between the data-strobe signal and the clock signal, wherein the write-read-validate operations involve varying a delay on the data-strobe signal relative to the clock signal by a multiple of a clock period.Type: GrantFiled: March 17, 2008Date of Patent: February 16, 2016Assignee: Rambus Inc.Inventors: Thomas J. Giovannini, Alok Gupta, Ian Shaeffer, Steven C. Woo
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Publication number: 20150324309Abstract: A memory space of a module connected to a memory controller via a memory interface may be used as a command buffer. Commands received by the module via the command buffer are executed by the module. The memory controller may write to the command buffer out-of-order. The memory controller may delay or eliminate writes to the command buffer. Tags associated with commands are used to specify the order commands are executed. A status buffer in the memory space of the module is used to communicate whether commands have been received or executed. Information received via the status buffer can be used as a basis for a determination to re-send commands to the command buffer.Type: ApplicationFiled: July 23, 2015Publication date: November 12, 2015Inventors: Liji Gopalakrishnan, Vlad Fruchter, Lawrence Lai, Pradeep Batra, Steven C. Woo, Wayne Frederick Ellis
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Patent number: 9177632Abstract: A system that calibrates timing relationships between signals involved in performing write operations is described. This system includes a memory controller which is coupled to a set of memory chips, wherein each memory chip includes a phase detector configured to calibrate a phase relationship between a data-strobe signal and a clock signal received at the memory chip from the memory controller during a write operation. Furthermore, the memory controller is configured to perform one or more write-read-validate operations to calibrate a clock-cycle relationship between the data-strobe signal and the clock signal, wherein the write-read-validate operations involve varying a delay on the data-strobe signal relative to the clock signal by a multiple of a clock period.Type: GrantFiled: May 18, 2015Date of Patent: November 3, 2015Assignee: Rambus Inc.Inventors: Thomas J. Giovannini, Alok Gupta, Ian Shaeffer, Steven C. Woo
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Patent number: 9165638Abstract: A system that calibrates timing relationships between signals involved in performing write operations is described. This system includes a memory controller which is coupled to a set of memory chips, wherein each memory chip includes a phase detector configured to calibrate a phase relationship between a data-strobe signal and a clock signal received at the memory chip from the memory controller during a write operation. Furthermore, the memory controller is configured to perform one or more write-read-validate operations to calibrate a clock-cycle relationship between the data-strobe signal and the clock signal, wherein the write-read-validate operations involve varying a delay on the data-strobe signal relative to the clock signal by a multiple of a clock period.Type: GrantFiled: May 1, 2015Date of Patent: October 20, 2015Assignee: Rambus Inc.Inventors: Thomas J. Giovannini, Alok Gupta, Ian Shaeffer, Steven C. Woo
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Publication number: 20150278506Abstract: Pairing data associated with a second device may be received at a first device. The pairing data may be received from a server. A first authentication proof may be generated based on the pairing data received from the server. A second authentication proof may be received from the second device. Furthermore, an authentication status of the second device may be updated based on a comparison of the first authentication proof that is based on the pairing data received from the server and the second authentication proof that is received from the second device.Type: ApplicationFiled: March 26, 2015Publication date: October 1, 2015Inventors: Benjamin Che-Ming Jun, Matthew Evan Orzen, Joel Patrick Wittenauer, Steven C. Woo
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Patent number: 9142281Abstract: A system that calibrates timing relationships between signals involved in performing write operations is described. This system includes a memory controller which is coupled to a set of memory chips, wherein each memory chip includes a phase detector configured to calibrate a phase relationship between a data-strobe signal and a clock signal received at the memory chip from the memory controller during a write operation. Furthermore, the memory controller is configured to perform one or more write-read-validate operations to calibrate a clock-cycle relationship between the data-strobe signal and the clock signal, wherein the write-read-validate operations involve varying a delay on the data-strobe signal relative to the clock signal by a multiple of a clock period.Type: GrantFiled: April 28, 2015Date of Patent: September 22, 2015Assignee: Rambus Inc.Inventors: Thomas J. Giovannini, Alok Gupta, Ian Shaeffer, Steven C. Woo
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Publication number: 20150255144Abstract: A system that calibrates timing relationships between signals involved in performing write operations is described. This system includes a memory controller which is coupled to a set of memory chips, wherein each memory chip includes a phase detector configured to calibrate a phase relationship between a data-strobe signal and a clock signal received at the memory chip from the memory controller during a write operation. Furthermore, the memory controller is configured to perform one or more write-read-validate operations to calibrate a clock-cycle relationship between the data-strobe signal and the clock signal, wherein the write-read-validate operations involve varying a delay on the data-strobe signal relative to the clock signal by a multiple of a clock period.Type: ApplicationFiled: April 28, 2015Publication date: September 10, 2015Applicant: Rambus Inc.Inventors: Thomas J. Giovannini, Alok Gupta, Ian Shaeffer, Steven C. Woo
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Publication number: 20150248926Abstract: A system that calibrates timing relationships between signals involved in performing write operations is described. This system includes a memory controller which is coupled to a set of memory chips, wherein each memory chip includes a phase detector configured to calibrate a phase relationship between a data-strobe signal and a clock signal received at the memory chip from the memory controller during a write operation. Furthermore, the memory controller is configured to perform one or more write-read-validate operations to calibrate a clock-cycle relationship between the data-strobe signal and the clock signal, wherein the write-read-validate operations involve varying a delay on the data-strobe signal relative to the clock signal by a multiple of a clock period.Type: ApplicationFiled: May 18, 2015Publication date: September 3, 2015Inventors: Thomas J. Giovannini, Alok Gupta, Ian Shaeffer, Steven C. Woo
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Publication number: 20150243343Abstract: A system that calibrates timing relationships between signals involved in performing write operations is described. This system includes a memory controller which is coupled to a set of memory chips, wherein each memory chip includes a phase detector configured to calibrate a phase relationship between a data-strobe signal and a clock signal received at the memory chip from the memory controller during a write operation. Furthermore, the memory controller is configured to perform one or more write-read-validate operations to calibrate a clock-cycle relationship between the data-strobe signal and the clock signal, wherein the write-read-validate operations involve varying a delay on the data-strobe signal relative to the clock signal by a multiple of a clock period.Type: ApplicationFiled: May 1, 2015Publication date: August 27, 2015Applicant: Rambus Inc.Inventors: Thomas J. Giovannini, Alok Gupta, Ian Shaeffer, Steven C. Woo
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Patent number: 9098209Abstract: A memory space of a module connected to a memory controller via a memory interface may be used as a command buffer. Commands received by the module via the command buffer are executed by the module. The memory controller may write to the command buffer out-of-order. The memory controller may delay or eliminate writes to the command buffer. Tags associated with commands are used to specify the order commands are executed. A status buffer in the memory space of the module is used to communicate whether commands have been received or executed. Information received via the status buffer can be used as a basis for a determination to re-send commands to the command buffer.Type: GrantFiled: October 27, 2013Date of Patent: August 4, 2015Assignee: Rambus Inc.Inventors: Liji Gopalakrishnan, Vlad Fruchter, Lawrence Lai, Pradeep Batra, Steven C. Woo, Wayne Frederick Ellis
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Patent number: 8935489Abstract: The disclosed embodiments relate to a system for processing memory references received from multiple processor cores. During operation, the system monitors the memory references to determine whether memory references from different processor cores are interfering with each other as the memory references are processed by a memory system. If memory references from different processor cores are interfering with each other, the system time-multiplexes the processing of memory references between processor cores, so that a block of consecutive memory references from a given processor core is processed by the memory system before memory references from other processor cores are processed.Type: GrantFiled: November 10, 2010Date of Patent: January 13, 2015Assignee: Rambus Inc.Inventors: Steven C. Woo, Trung A. Diep, Michael T. Ching
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Patent number: 8838900Abstract: A cache-coherence protocol distributes atomic operations among multiple processors (or processor cores) that share a memory space. When an atomic operation that includes an instruction to modify data stored in the shared memory space is directed to a first processor that does not have control over the address(es) associated with the data, the first processor sends a request, including the instruction to modify the data, to a second processor. Then, the second processor, which already has control of the address(es), modifies the data. Moreover, the first processor can immediately proceed to another instruction rather than waiting for the address(es) to become available.Type: GrantFiled: June 10, 2013Date of Patent: September 16, 2014Assignee: Rambus Inc.Inventors: Qi Lin, Liang Peng, Craig E. Hampel, Thomas J. Sheffler, Steven C. Woo, Bohuslav Rychlik
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Publication number: 20140201431Abstract: Nonvolatile memory (e.g., flash memory, solid-state disk) is included on memory modules that are on a DRAM memory channel. Nonvolatile memory residing on a DRAM memory channel may be integrated into the existing file system structures of operating systems. The nonvolatile memory residing on a DRAM memory channel may be presented as part or all of a distributed file system. Requests and/or remote procedure call (RPC) requests, or information associated with requests and/or RPCs, may be routed to the memory modules over the DRAM memory channel in order to service compute and/or distributed file system commands.Type: ApplicationFiled: February 23, 2014Publication date: July 17, 2014Applicant: Rambus Inc.Inventor: Steven C. Woo
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Patent number: 8665642Abstract: A method of operating a memory device includes receiving first and second sets of bits to be stored in multi-level cells in the device. A multi-level encoding is selected from among a plurality of multi-level encodings for storing the first and second sets of bits in the multi-level cells. Each multi-level encoding includes at least four encoding levels for a respective multi-level cell. Respective multi-level encodings have respective costs associated with programming the first and second sets of bits into the multi-level cells in accordance with the respective multi-level encodings. The multi-level encoding is selected based on the respective costs of the respective encodings. The first and second sets of bits are encoded in accordance with the selected multi-level encoding to produce encoded data for storage in the device such that a respective multi-level cell stores respective bits from both the first and second sets of bits.Type: GrantFiled: October 8, 2009Date of Patent: March 4, 2014Assignee: Rambus Inc.Inventors: Bohuslav Rychlik, John Eric Linstadt, Brent Steven Haukness, Steven C. Woo
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Publication number: 20130275663Abstract: A cache-coherence protocol distributes atomic operations among multiple processors (or processor cores) that share a memory space. When an atomic operation that includes an instruction to modify data stored in the shared memory space is directed to a first processor that does not have control over the address(es) associated with the data, the first processor sends a request, including the instruction to modify the data, to a second processor. Then, the second processor, which already has control of the address(es), modifies the data. Moreover, the first processor can immediately proceed to another instruction rather than waiting for the address(es) to become available.Type: ApplicationFiled: June 10, 2013Publication date: October 17, 2013Inventors: Qi Lin, Liang Peng, Craig E. Hampel, Thomas J. Sheffler, Steven C. Woo, Bohusluv Rychlik
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Publication number: 20130194881Abstract: One or more pins may be modally assigned to either the command/address (C/A) or data (DQ) blocks of a uniform-package, multi-modal PHY (physical signaling interface) of a memory controller, thus enabling those pins to be used as C/A pins when the PHY is connected to some memory types, and as DQ pins when the PHY is connected to other memory types.Type: ApplicationFiled: November 7, 2011Publication date: August 1, 2013Inventors: Steven C. Woo, Amir Amirkhany, Catherine Chen, David Secker, Jie Shen
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Patent number: 8473681Abstract: A cache-coherence protocol distributes atomic operations among multiple processors (or processor cores) that share a memory space. When an atomic operation that includes an instruction to modify data stored in the shared memory space is directed to a first processor that does not have control over the address(es) associated with the data, the first processor sends a request, including the instruction to modify the data, to a second processor. Then, the second processor, which already has control of the address(es), modifies the data. Moreover, the first processor can immediately proceed to another instruction rather than waiting for the address(es) to become available.Type: GrantFiled: February 2, 2010Date of Patent: June 25, 2013Assignee: Rambus Inc.Inventors: Qi Lin, Liang Peng, Craig E. Hampel, Thomas J. Sheffler, Steven C. Woo, Bohuslav Rychlik
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Patent number: 8407441Abstract: A system that calibrates timing relationships between signals involved in performing write operations is described. This system includes a memory controller which is coupled to a set of memory chips, wherein each memory chip includes a phase detector configured to calibrate a phase relationship between a data-strobe signal and a clock signal received at the memory chip from the memory controller during a write operation. Furthermore, the memory controller is configured to perform one or more write-read-validate operations to calibrate a clock-cycle relationship between the data-strobe signal and the clock signal, wherein the write-read-validate operations involve varying a delay on the data-strobe signal relative to the clock signal by a multiple of a clock period.Type: GrantFiled: May 19, 2011Date of Patent: March 26, 2013Assignee: Rambus Inc.Inventors: Thomas J. Giovannini, Alok Gupta, Ian Shaeffer, Steven C. Woo
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Patent number: 8332556Abstract: A memory bus with a first bus segment coupled to a memory controller that includes control logic and a first memory device, a second bus segment coupled to a second memory device, and a switch between the first bus segment and the second bus segment. The control logic outputs control information to the switch to selectively decouple the first bus segment and the second bus segment to effect a change in the length of the memory bus to enable data transfer with respect to the first memory device at a first data rate. Additionally, the control logic may output control information to the switch to selectively couple the first bus segment and the second bus segment to increase the length of the memory bus to enable data transfer with respect to the second memory device at a second data rate that is slower than the first data rate.Type: GrantFiled: January 12, 2012Date of Patent: December 11, 2012Assignee: Rambus Inc.Inventors: Steven C. Woo, Scott C. Best
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Publication number: 20120278583Abstract: The disclosed embodiments relate to a system for processing memory references received from multiple processor cores. During operation, the system monitors the memory references to determine whether memory references from different processor cores are interfering with each other as the memory references are processed by a memory system. If memory references from different processor cores are interfering with each other, the system time-multiplexes the processing of memory references between processor cores, so that a block of consecutive memory references from a given processor core is processed by the memory system before memory references from other processor cores are processed.Type: ApplicationFiled: November 10, 2010Publication date: November 1, 2012Applicant: RAMBUS INC.Inventors: Steven C. Woo, Trung A. Diep, Michael T. Ching