Abstract: A readout circuit for use with a focal plane array that employs a single transistor in each unit cell and a single capacitive feedback transimpedance amplifier to process the outputs of each column of detector elements of the array. The capacitive feedback transimpedance amplifiers extract the signals associated with the pixels along a particular row of the array. The present invention permits high performance readouts to be constructed with very little circuitry in the unit cells. Only a single minimum sized transistor switch is required in each unit cell to perform readout and reset functions for the array. In the disclosed embodiment, the readout circuit comprises an array of unit cells, each cell comprising a detector input circuit, a single transistor and a single charge storage capacitor. Row address circuits are coupled to the cells in each row of the array. A plurality of capacitive feedback transimpedance amplifiers are coupled to the cells in each column of the array.

Abstract: A transistorized monolithic focal plane array is formed on a semiconductive substrate and comprises a plurality of detectors associated with a corresponding plurality of source follower or inverter transistors. The array is row addressable. The gate of the source follower transistor comprises a floating node which is charged by the corresponding detector in proportion to the incident photon flux, the gate being periodically reset. The invention combines the advantages of compactness and low capacitance of charge coupled device imagers and low noise characteristics of prior art imagers comprising discrete transistors.