Abstract: A computer system consisting of a host processor, memory and peripheral devices coupled via a bus which provides emulation of a microprocessor by coupling the microprocessor to the bus. The host processor provides emulation of microprocessor peripherals such that a microprocessor based system is supported and executes processes. A takeover mechanism is provided to enable the host processor to temporarily takeover the microprocessor to perform certain tasks. The host processor causes an interrupt to occur in the microprocessor and monitors the bus cycles initiated by the microprocessor to determine when the microprocessor performs fetches of the routine to service the interrupt. The host processor intercepts fetches for information regarding the location of the interrupt service routine and provides information that causes the microprocessor to execute code of a process to be executed during the takeover. For example, during the takeover, noninvasive debugging of the microprocessor can be performed.

Abstract: A method is provided for writing directly to a frame buffer which provides signals to an output display of a computer system. The computer system has a first processor running a window management program controlling the furnishing of data in a first format to the frame buffer, and a second processor running application programs in a second format for display. A signal is provided from the second processor to the window management program indicating that an application program running on the second processor has information to be displayed. Then a window is set up for the display of the application program running on the second processor under control of the window management program. The second processor is signaled that the window exists and provided information regarding the position and clipping of the window.

Abstract: In the system of the present invention, a specialized form of read-ahead, write-behind buffering is provided which enables the host processing system to provide timely responses to device requests that are emulated by the host processor. Each input/output device request is identified by an address to which the device is purportedly mapped to. This address is translated to an address containing a status word for that particular device being emulated. Each status word contains a byte of information either to be sent to the microprocessor as a response during an I/O read operation request by the microprocessor, or to receive data written by the microprocessor in response to an I/O write operation request, and a plurality of status bits which identify the state of the data contained in the I/O status word.

Abstract: A DRAM allows for hidden refresh of its memory cells. The refresh is performed during a refresh cycle at the beginning of a clock cycle. Immediately before the beginning of each clock cycle the DRAM selects a word line for a row of memory cells for which a data access is to be performed. The DRAM also selects at least one word line for at least one row of memory cells for which a refresh is to be performed. During the refresh cycle, a refresh is performed on every memory cell row which is selected for data access or which is selected for refresh. After the refresh cycle, during a data access segment of the clock cycle, the DRAM continues to select the word line for the row of memory cells for which a data access is to be performed; however, the DRAM no longer selects the at least one word line for at the least one row of memory cells selected for refresh. During the data access segment of the clock cycle, the data access is performed on the row of memory cells which remain selected.

Abstract: A multi-input logic gate is disclosed having particular application for use as an AND or OR gate in a digital circuit. The OR gate of the present invention includes drive, sense and reference rails. A plurality of input lines are coupled to a gate of a plurality of N-channel transfers disposed between the drive and sense rails, one input line per transistor. The drive rail is coupled to ground through an N-channel transistor whose gate is controlled by the state of a detect line. The sense and reference rails are coupled to a voltage source (V.sub.dd) through P-channel transistors whose gate is also coupled to the detect line. The P-channel transistor coupled to the sense rail is sized to pass more current than the corresponding transfer on the reference rail. A sense amplifier is coupled to the sense and reference rails, and outputs a predetermined signal as a function of the voltage difference of the rails.

Abstract: Apparatus and methods are disclosed for providing an increased flexibility and rate in processing data in a random access memory (RAM) system. The apparatus comprises, in a first embodiment, a switching circuit which is coupled to the word lines of the RAM array and which is selectively operable in two modes. The switching circuit operates in a first mode to transmit word line signals to a single row of memory cells in the RAM array in accordance with principles well known in the prior art. The switching circuit is responsive to a control circuit, and operates in a second mode to alter, along the row of memory cells in the RAM array, the word line signal path, to provide simultaneous accessing of portions of at least two adjacent rows of memory cells in the RAM array. Such simultaneous accessing allows the processing of more data through the memory system that was previously possible in accordance with principles known in the prior art.

Abstract: Methods and apparatus are disclosed for inhibiting the unauthorized copying of ROM-resident computer software or the like, for example, the audio-visual display of an electronic video game. A protection circuit including encryption/decryption means is coupled between the microprocessor and the ROM-memory and is operable in a first mode to properly encrypt/decrypt the program information according to a first algorithm and in a second mode to prevent proper encryption/decryption. The address-data buses are monitored by the protection circuit to detect an invalid program event, such as may occur when a microprocessor emulator is used to attempt an unauthorized copying or "dumping" of the program information. Upon detection of the invalid program event or "trap condition", the protection circuit switches to its second operating mode thereby to prevent copying of the decrypted program information.