Abstract: A system and method for providing antialiased memory access includes receiving a request to access a memory address. The memory address is examined to determine if the memory address is within a virtual frame buffer. If the memory address is within a virtual frame buffer then the memory address is transformed into one or more physical addresses within a frame buffer that is utilized for antialiasing. The frame buffer may be a single memory space containing subpixel information corresponding to pixels of the virtual frame buffer. Subpixels located at the physical addresses within the frame buffer are then accessed. The disclosed invention provides for direct access by a software application.

Abstract: Circuits, methods, and apparatus that reduce the amount of data transferred between a graphics processor integrated circuit and graphics memory. Various embodiments of the present invention further improve the efficiency of blenders that are included on a graphics processor. One embodiment provides for the storage of a reduced number of subsamples of a pixel when the storage of a larger number of subsamples would be redundant. The number of subsamples that are blended with source data are compressed, thereby reducing the task load on the blenders increasing their efficiency. These methods can be disabled to avoid errors that may arise in certain applications.

Abstract: A tiled graphics memory permits graphics data to be stored in different tile formats. One application is selecting a tile format optimized for the data generated for particular graphical surfaces in different rendering modes. Consequently, the tile format can be selected to optimize memory access efficiency and/or packing efficiency. In one embodiment a first tile format stores pixel data in a format storing two different types of pixel data whereas a second tile format stores one type of pixel data. In one implementation, a z-only tile format is provided to store only z data but no stencil data. At least one other tile format is provided to store both z data and stencil data. In one implementation, z data and stencil data are stored in different portions of a tile to facilitate separate memory accesses of z and stencil data.

Abstract: A memory system having a number of partitions each operative to independently service memory requests from a plurality of memory clients while maintaining the appearance to the memory client of a single partition memory subsystem. The memory request specifies a location in the memory system and a transfer size. A partition receives input from an arbiter circuit which, in turn, receives input from a number of client queues for the partition. The arbiter circuit selects a client queue based on a priority policy such as round robin or least recently used or a static or dynamic policy. A router receives a memory request, determines the one or more partitions needed to service the request and stores the request in the client queues for the servicing partitions.

Abstract: A z buffer stores compressed z data represented in a planar format for one or more tiles. The compressed format includes a set of tile specific coefficients defining a plane equation for each z tested primitive intersecting the tile. The z buffer stores a maximum number of sets of tile specific coefficients for each tile, and when the maximum number of sets is exceeded for a particular tile, an uncompressed format is used to store the z data for the particular tile.

Abstract: A memory system having a number of partitions each operative to independently service memory requests from a plurality of memory clients while maintaining the appearance to the memory client of a single partition memory subsystem. The memory request specifies a location in the memory system and a transfer size. A partition receives input from an arbiter circuit which, in turn, receives input from a number of client queues for the partition. The arbiter circuit selects a client queue based on a priority policy such as round robin or least recently used or a static or dynamic policy. A router receives a memory request, determines the one or more partitions needed to service the request and stores the request in the client queues for the servicing partitions.

Abstract: A graphics system has a mode of operation in which real samples and virtual samples are generated for anti-aliasing pixels. Each virtual sample identifies a set of real samples associated with a common primitive that covers a virtual sample location within a pixel. The virtual samples provide additional coverage information that may be used to adjust the weights of real samples.

Abstract: A tiled graphics memory permits z data and stencil data to be stored in different portions of a tile. The tile may be further divided into data sections, each of which may have a byte size corresponding to a memory access size.

Abstract: Prior to executing a program on a fragment, a conflict detection unit, within a fragment processor checks if there is a position conflict indicating a RAW (read after write) hazard may exist. A RAW hazard exists when there is a pending write to a destination location that source data will be read from during execution of the program. When the fragment enters a processing pipeline, each destination location that may be written during the processing of the fragment is entered in conflict detection unit. During processing, the conflict detection unit is updated when a pending write to a destination location is completed.

Abstract: Apparatuses and methods for detecting position conflicts during fragment processing are described. Prior to executing a program on a fragment, a conflict detection unit, within a fragment processor checks if there is a position conflict indicating a RAW (read after write) hazard may exist. A RAW hazard exists when there is a pending write to a destination location that source data will be read from during execution of the program. When the fragment enters a processing pipeline, each destination location that may be written during the processing of the fragment is entered in conflict detection unit. During processing, the conflict detection unit is updated when a pending write to a destination location is completed.

Abstract: A graphics pipeline system and method are provided for graphics processing. Such system includes a transform module adapted for receiving graphics data. The transform module serves to transform the graphics data from a first space to a second space. Coupled to the transform module is a lighting module which is positioned on the single semiconductor platform for performing lighting operations on the graphics data received from the transform module. Also included is a rasterizer coupled to the lighting module and positioned on the single semiconductor platform for rendering the graphics data received from the lighting module. During use, an antialiasing feature is implemented on the single semiconductor platform to improve a quality of the graphics rendering.

Abstract: A system and method are provided for generating multiple output packets in a single processing pass of a shader in a hardware graphics pipeline. Initially, graphics data is received, after which it is processed utilizing the shader of the hardware graphics pipeline to generate a plurality of output packets. The plurality of output packets is outputted from the shader of the hardware graphics pipeline in the single processing pass.

Abstract: Hybrid sampling of pixels of an image involves generating shading values at multiple shading sample locations and generating depth values at multiple depth sample locations, with the number of depth sample locations exceeding the number of shading sample locations. Each shading sample location is associated with one or more of the depth sample locations. Generation and filtering of hybrid sampled pixel data can be done within a graphics processing system, transparent to an application that provides image data.

Abstract: A programmable graphics system and method for processing high precision graphics data represented in one or more data formats in one or more passes. Graphics program instructions executed by the system control the processing and format conversion of the data. The program instructions and the data are stored in a memory accessible by the system. Within the memory, contiguous memory entries can contain program instructions or data represented in different formats. The format used to represent a particular data element within the data, is specified in the state information maintained in the system and is used to configure format conversion units within the system. High precision data, such as floating color, is processed by the programmable graphics system and output via a digital to analog converter (DAC) for display.

Abstract: A memory system having a number of partitions each operative to independently service memory requests from a plurality of memory clients while maintaining the appearance to the memory client of a single partition memory subsystem. The memory request specifies a location in the memory system and a transfer size. A partition receives input from an arbiter circuit which, in turn, receives input from a number of client queues for the partition. The arbiter circuit selects a client queue based on a priority policy such as round robin or least recently used or a static or dynamic policy. A router receives a memory request, determines the one or more partitions needed to service the request and stores the request in the client queues for the servicing partitions.

Abstract: A system and method are provided for the compression of pixel data for communicating the same with a frame buffer. Initially, a plurality of samples is received. It is first determined whether the samples are reducible, in that a single sample value can take the place of a plurality of sample values. If it is determined that the samples are capable of being reduced, the samples are reduced. Reduction is a first stage of compression. It is then determined whether the samples are capable of being compacted. The samples are then compacted if it is determined that the samples are capable of being compacted. Compaction is a second stage of compression. The samples are then communicated with a frame buffer, in compressed form, if possible, in uncompressed form if not. Subsequent reading of frame buffer data takes advantage of the smaller transfer size of compressed data. Compressed data is uncompacted and expanded as necessary for further processing or display.

Abstract: A programmable graphics system and method for processing high precision graphics data represented in one or more data formats in one or more passes. Graphics program instructions executed by the system control the processing and format conversion of the data. The program instructions and the data are stored in a memory accessible by the system. Within the memory, contiguous memory entries can contain program instructions or data represented in different formats. The format used to represent a particular data element within the data, is specified in the state information maintained in the system and is used to configure format conversion units within the system. High precision data, such as floating color, is processed by the programmable graphics system and output via a digital to analog converter (DAC) for display.

Abstract: A graphics pipeline system and method are provided for graphics processing. Such system includes a transform module adapted for receiving graphics data. The transform module serves to transform the graphics data from a first space to a second space. Coupled to the transform module is a lighting module which is positioned on the single semiconductor platform for performing lighting operations on the graphics data received from the transform module. Also included is a rasterizer coupled to the lighting module and positioned on the single semiconductor platform for rendering the graphics data received from the lighting module. During use, an antialiasing feature is implemented on the single semiconductor platform to improve a quality of the graphics rendering.

Abstract: A graphics pipeline system is provided for graphics processing. Such system includes a transform module adapted for receiving vertex data. The transform module serves to transform the vertex data from a first space to a second space. Coupled to the transform module is a lighting module which is positioned on the single semiconductor platform for performing lighting operations on the vertex data received from the transform module. Also included is a rasterizer coupled to the lighting module and positioned on the single semiconductor platform for rendering the vertex data received from the lighting module. During use, an antialiasing feature is implemented to improve a quality of the graphics rendering.

Abstract: A system for image generation comprising a plurality of renderers, each having a geometry processor and a rasterizer, that operate in parallel to compute pixel values for a set of primitive objects that comprise the image to be rendered. The geometry processor transforms graphics primitive objects from their native object coordinates to screen coordinates. The rasterizer consists of an array of enhanced memory devices having a processor and memory for each pixel in a region of a screen. The processors and their associated memories operate in SIMD fashion on screen space primitive descriptions to compute and store pixel values for an entire such region. The enhanced memory devices further comprise compositors for combining their pixel values, for example, based on a visibility test, with those from a corresponding memory device of another rasterizer.