Abstract: A communication device including a plurality of frequency synthesizers (24, 28, 30). At least one of the frequency synthesizers (24) is driven with a reference frequency from a crystal oscillator (58). The at least one frequency synthesizer (24) includes a phase locked loop with a fractional-N divider (48) which is programmed by a control circuit (64) to vary as a function of temperature compensation, frequency compensation, and a frequency multiplication factor. The output (46) of the at least one frequency synthesizer (24) is used to provide a compensated reference frequency input for the remaining frequency synthesizers (28, 30). The radio provides all the frequency synthesizers (24, 28, 30) with temperature and frequency compensation using a reference frequency from a crystal oscillator (58) and only one high resolution frequency compensating synthesizer (24).

Abstract: A frequency synthesizer (10) including a synthesizer loop (12) with a fractional-N divider (14), and including a divider control circuit (18) and a combining circuit (22). The divider control circuit (18) provides a variable divide value (20) to the divider (14). The carry values of two accumulators (24, 26) having differing accumulator lengths are applied in parallel to the combining circuit (22). Each of the accumulators (24, 26) provides a portion of a desired fractional divide value (20). The combining circuit (22) also adds an integer divide value (36) to the fractional divide value (16). By coupling the accumulators (24, 26) in parallel, a high frequency resolution with minimal spurious frequencies is achieved, using a simple, low cost circuit.

Abstract: A frequency synthesizer (200) with temperature compensation and frequently multiplication. The synthesizer (200) having a temperature uncompensated frequency oscillator (202) coupled to a phase locked loop (206) including at least one temperature compensating and frequency multiplication element (208). The element (208) preferably being a multi-modulus divider. The element (208) is programmed by a control circuit (210) to vary as a function of temperature and to vary as a function of a fractional frequency multiplication factor. The element (208) also may provide adjustment of the nominal frequency of the frequency oscillator (202). The frequency oscillator (202) and preferably all the elements of the synthesizer (200) are temperature compensated by the element (208) to produce a temperature stable multiplied output frequency (238).

Abstract: A sample circuit (10) maintains linear operation over frequency. A switchable diode bridge (12) passes the analog input signal when enabled to one terminal of a sample storage capacitor (14). The second terminal of the capacitor is coupled through a closed FET switch (16) to a reference node (18). Once the analog input signal is stored across the capacitor, the FET switch opens before the diode bridge disables. When the second terminal of the capacitor floats and prevents any further charge from altering the sample voltage across the capacitor. When the diode bridge is disabled, the sample voltage across the capacitor does not change. The sample voltage may be amplified and digitized for further processing in the cellular system.

Abstract: A transmitter has an oscillator (101, 201, 303, 401, 501) that operates at frequency k multiplied by f.sub.c, thus the oscillator (101, 201, 303, 401, 501) outputs a signal at an output frequency, kf.sub.c. Coupled to the oscillator (101, 201, 303, 401, 501) is a frequency modifier (103, 205, 307, 405, 505), for modifying the oscillator output frequency by factor 1/k, thereby producing a signal at frequency f.sub.c at the frequency modifier output. Coupled to the frequency modifier output is a modulator (105, 215, 301, 407-417, 507-517) for producing a modulated output signal substantially centered at frequency f.sub.c.

Abstract: An improved phase synchronization circuit (301) and method therefor for a phase locked loop (300). Each of a divided reference frequency signal (206) and a feedback signal (209) is held in a predetermined state. The divided reference frequency signal (206) is enabled responsive to the phase of a reference frequency signal (115). A phase relationship between the reference frequency signal (115) and an output frequency signal (116 or 117) is determined. The feedback signal (209) is enabled responsive to enabling the divided reference frequency signal (206) and the determined phase relationship. The present invention advantageously provides a rapid and accurate phase synchronization for the PLL (300) with minimum additional hardware and without introducing phase error into the PLL (300).

Abstract: A cellular cordless telephone (10) operates with both a cordless base station (180) and a cellular base station (190) and cellular control terminal (196). In one embodiment (FIG. 2 ), a cellular cordless telephone (100) includes a cellular transceiver (120), antenna (128), keyboard (140), a display (180), handset (160), and microcomputer (130) together with a cordless transceiver (110) and antenna (118), all of which may be in a single housing. In another embodiment (FIG. 3 ), a cellular cordless telephone (200) includes a cellular telephone (220) and a cordless telephone transceiver (210) which may be a plugable module. Whenever cellular cordless telephone (10) is within range of cordless base station (180), telephone calls may be made over the cordless radio channel or transferred from the cellular radio channels to the cordless radio channel.

Abstract: An apparatus and method for operating a phase locked loop frequency synthesizer responsive to radio frequency channel spacing. The phase locked loop (PLL) frequency synthesizer (300) tunes a radio frequency transceiver (100) to a radio frequency channel. A processor (110) in the transceiver (100) determines the channel spacing of the radio frequency channels in a portion of a radio frequency band including the radio frequency channel, and controls the PLL frequency synthesizer (300) responsive to the determined channel spacing. The present invention advantageously provides the PLL frequency synthesizer (300) with faster lock time and lower noise.

Abstract: A phase lock loop (PLL) frequency synthesizer is used in a radiotelephone to provide a reference frequency to a transmitter or a receiver. This particular PLL frequency synthesizer has a wide bandwidth control loop having a high current charge pump (417) and a narrow bandwidth control loop having a low current charge pump (411). A deadzone circuit (413) is used at an output of a phase detector (405) to control the application of an error signal to the high current charge pump (417). Additionally, the PLL frequency synthesizer utilizes a loop filter (419). The loop filter (419) receives two correction signals (409', 415') and provides a single control signal for the VCO (voltage controlled oscillator) (423). The loop filter contains two time constants formed from resistive and capacitive elements. The two time constants control the bandwidth of the two control loops.

Abstract: A transimpedance circuit (201), and method therefor, frequency compensates an operational amplifier. The transimpedance circuit (201) has an input terminal (205) coupled to receive an amplified signal (205) and an ouput terminal (206) operative to produce a buffered amplified signal. The input terminal (205) of the transimpedance circuit (201) presents a resistive input impedance to the amplified signal at a frequency substantially near an open loop unity gain frequency of the operational amplifier (200). The amplified signal is buffered from a complex impedance of an input terminal (206) of an output driver (103). The present invention advantageously provides wide bandwidth and stable operation with loads having low complex impedance.

Abstract: A quadrant generator for generating a pair of pulse trains maintained in perfect phase quadrant with one another. The quadrature generator includes a feedback control loop for altering the duty cycle of an oscillating signal applied to a master-slave flip-flop pair configured to generate a pair of pulse trains maintained in a relative phase relationship. The feedback control loop controls the duty cycle of the oscillating signal applied to the master-slave flip-flop pair which, in turn, is determinative of the phase relationship between the pulse train pair generated by the master-slave flip-flop pair. When the pulse trains generated by the flip-flop pair are beyond phase quadrature, a control signal generated by the feedback control loop alters the duty cycle of the oscillating signal applied to the flip-flop pair to alter the phase relationship between the pulse trains of the pulse train pair.

Abstract: A cellular cordless telephone (10) operates with both a cordless base station (180) and a cellular base station (190) and cellular control terminal (196). In one embodiment (FIG. 2), a cellular cordless telephone (100) includes a cellular transceiver (120), antenna (128), keyboard (140), a display (180), handset (160), and microcomputer (130) together with a cordless transceiver (110) and antenna (118), all of which may be in a single housing. In another embodiment (FIG. 3), a cellular cordless telephone (200) includes a cellular telephone (220) and a cordless telephone transceiver (210) which may be a plugable module. Whenever cellular cordless telephone (10) is within range of cordless base station (180), telephone calls may be made over the cordless radio channel or transferred from the cellular radio channels to the cordless radio channel.

Abstract: A current mirror having improved turn-on and turn-off characteristics capable of operation an expanded voltage range. A cascode circuit comprising a portion of the current mirror is of a high characteristic impedance to increase thereby the voltages over which the current mirror may generate a constant current output. A switching circuit comprised of tandemly-positioned transistors having differing transistor characteristics decreases the transistor turn-on and turn-off times to enhance the characteristics of the current mirror.

Abstract: A cellular cordless telephone (10) operates with both a cordless base station (180) and a cellular base station (190) and cellular control terminal (196). In one embodiment (FIG. 2) , a cellular cordless telephone (100) includes a cellular transceiver (120), antenna (128), keyboard (140), a display (180), handset (160), and microcomputer (130) together with a cordless transceiver (110) and antenna (118), all of which may be in a single housing. In another embodiment (FIG. 3), a cellular cordless telephone (200) includes a cellular telephone (220) and a cordless telephone transceiver (210) which may be a plugable module. Whenever cellular cordless telephone (10) is within range of cordless base station (180), telephone calls may be made over the cordless radio channel or transferred from the cellular radio channels to the cordless radio channel.

Abstract: A fractional-division synthesizer for a digital transceiver is disclosed in which the fractional divisor may be separated into an integer, N, and a fraction made up of two integers, [n/d]. The integer n is the numerator of the fraction part of the fractional divisor. The integer N is the whole number portion of the fractional divisor. The integer d multiplied by the value of the transceiver channel spacing is algebraically related to the frequency of the reference oscillator. A bit rate clock is also derived from the reference oscillator.

Abstract: A .pi./4-shift DQPSK modulator modulates a digitized voice signal and other information. An FM modulator modulates the analog voice signal and other information. The FM modulator is coupled to the quadrature mixers (109 and 110) of the .pi./4-shift DQPSK modulator. When an FM modulated signal is required, the mixers (109 and 110) are biased (114) to allow carrier feedthrough by applying a fixed, non-zero DC signal to one or both mixers (109 and 110). The carrier is then FM modulated using conventional methods such as voltage-modulation of a phase locked loop (PPL) (113). When .pi./4-shift DQPSK is to be generated, the conventional baseband I and Q vector-length signals (101 and 102) are applied to the mixers (109 and 110), and the carrier is left unmodulated by switching (115) out the input signal to the PLL (113). The PPL (113) will then generate only the carrier frequency to be mixed with the I and Q vector-length signals (101 and 102).

Abstract: A cellular cordless telephone (10) operates with both a cordless base station (180) and a cellular base station (190) and cellular control terminal (196). In one embodiment (FIG. 2), a cellular cordless telephone (100) includes a cellular transceiver (120), antenna (128), keyboard (140), a display (180), handset (160), and microcomputer (130) together with a cordless transceiver (110) and antenna (118), all of which may be in a single housing. In another embodiment (FIG. 3), a cellular cordless telephone (200) includes a cellular telephone (220) and a cordless telephone transceiver (210) which may be a plugable module. Whenever cellular cordless telephone (10) is within range of cordless base station (180), telephone calls may be made over the cordless radio channel or transferred from the cellular radio channels to the cordless radio channel.

Abstract: A linearized three state phase detector (300) that exhibits a linear transfer function of phase to current or charge at and around the zero phase error region. The inputs to the D flip-flops (301 and 302) are tied to a logic high. the first flip-flop (301) is clocked with reference signal F.sub.r while the other flip-flop (302) is clocked with a variable frequency feedback signal F.sub.v. F.sub.v is typically from a voltage controlled oscillator in a phase locked loop. The outputs of the flip-flops are ANDed together with the result of this operation going through a delay element (304) before reseting one of the flip-flops (301). The other flip-flop (302) is reset by the output of the AND gate (304) without the delay element (304). Each flip-flop output enables a charge pump--one negative polarity (306) and one positive polarity (305).

Abstract: A continuously adaptive phase locked loop synthesizer is disclosed in which error correction pulses from a phase detector are separated into narrow pulse width and wide pulse width pulses. The wide pulse width pulses are coupled to the loop filter to enable a rapid charge of the loop filter to provide a VCO control voltage on a control line connected to the output of the loop filter. The narrow pulse width pulses are filtered by a narrow bandwidth filter before being applied to the loop filter thus enabling a slow charge of the loop filter. The narrow bandwidth filter is decoupled from the control line but referenced to the control line voltage.

Abstract: A unique automatic battery charger (100) is described that recharges a battery (202) including a thermistor (206) for sensing the battery temperature. The charger (100) produces both a slow-charge current and a fast-charge current. Upon detecting the presence of the battery (202), the unique charger (100) turns on a fast-charge current produced by a switchable current source (110-113). The fast-charge current is subsequently turned off when the battery (202) is fully charged as indicated by the status of monitored temperature and voltage conditions. Comparators (180-184) are utilized to monitor these voltage and temperature conditions. According to a novel feature of the present invention, the monitored temperature thresholds are changed in response to the supply voltage. The automatic battery charging apparatus of the present invention may be advantageously utilized in a variety of applications for rapidly and safely charging batteries used in battery-operated electrical apparatus.