Abstract: A processing system includes one or more power supply monitors (PSMs) to measure one or more first voltages corresponding to one or more locations in the processing system. The measurements are performed concurrently with the processing system executing one or more code loops. The processing system also includes calibration logic to modify a second voltage provided to the processing system based on a comparison of a reference voltage and the one or more first voltages. The reference voltage is determined based on previous execution of the one or more code loops by the processing system.

Abstract: A processing system includes one or more power supply monitors (PSMs) to measure one or more first voltages corresponding to one or more locations in the processing system. The measurements are performed concurrently with the processing system executing one or more code loops. The processing system also includes calibration logic to modify a second voltage provided to the processing system based on a comparison of a reference voltage and the one or more first voltages. The reference voltage is determined based on previous execution of the one or more code loops by the processing system.

Abstract: A processor comprises a processor core and a controller. The processor core has an execution unit configured to execute instructions and to attempt to perform at least one operation in executing one of the instructions. The processor core is configured to detect a processor error associated with the at least one operation. The controller is configured to change an operating point of the processor core in response to a detection of the processor error such that the processor core operates at a new operating point, and the processor core is configured to retry the at least one operation while the processor core is operating at the new operating point.

Abstract: One disclosed embodiment may comprise an interpolation system that includes an interpolator that interpolates between a selected phase from a preceding cycle and a selected phase from a current cycle to provide an interpolated phase for the current cycle. An edge of the interpolated phase for the current cycle has reduced jitter relative to an edge of a corresponding phase of the current cycle. A delay system delays a plurality of other phases of the current cycle to provide delayed other phases, the delayed other phases and the interpolated phase for the current cycle collectively defining a set of adjusted phases for the current cycle.

Abstract: Techniques are disclosed for increasing reliability of an integrated circuit. In one embodiment, an integrated circuit includes core chip circuitry. The integrated circuit includes means for increasing a power supply voltage V provided to the core chip circuitry, such as by increasing the voltage V to a maximum value. The integrated circuit also includes means for identifying a clock frequency F for which F<Pmax/(CV2), where C is a switching capacitance and where Pmax is a predetermined maximum power consumption of the core chip circuitry. The integrated circuit also includes means for providing a clock signal having frequency F to the circuit.

Abstract: A processor comprises a processor core and a controller. The processor core has an execution unit configured to execute instructions and to attempt to perform at least one operation in executing one of the instructions. The processor core is configured to detect a processor error associated with the at least one operation. The controller is configured to change an operating point of the processor core in response to a detection of the processor error such that the processor core operates at a new operating point, and the processor core is configured to retry the at least one operation while the processor core is operating at the new operating point.

Abstract: The present invention relates to a system and method for adaptively adjusting delays along selected signal paths in order to equalize the signal delays at various distributed points within an integrated circuit. Where a signal traverses an initial outgoing path and a return path, delay elements disposed in each of the paths may be adjusted in order to set the entirety of the delay of the signal having traveled the entire signal trajectory equal to the delay present in a deliberately introduced delay element of known value. Alternatively, the inventive mechanism may control a selected one of two (or other plurality of) delay elements so as to automatically and adaptively adjust the delay value of the selected delay element so as to equalize the signal delay incurred along two or more signal paths.

Abstract: A method and apparatus for increasing the amount of memory available to a host device that utilizes flash memory are disclosed. In a preferred embodiment, a flash card comprising flash memory and a transmitter for transmitting data via wireless communication is utilized within a host device. Such flash card may store data in its flash memory, and may transmit data from the flash card to an extended storage device via wireless communication. In a preferred embodiment, such wireless communication is radio frequency (RF). Data transfer from the flash card to an extended storage device may be initiated by a mechanism on the flash card or on the host device. In a preferred embodiment, the flash card further comprises a receiver for receiving wireless signals. In such an embodiment, an extended storage device may initiate a data transfer by transmitting the appropriate signals to the flash card.

Abstract: The inventive recessed bezel or faceplate allows the tape drive to be recessed within the computer case such that the tape cartridge no longer protrudes from the front of the computer case. The inventive bezel uses finger cavities and a guide mechanism to facilitate tape cartridge insertion and removal.

Abstract: A switching power supply that uses the intrinsic series resistance of an output bypass capacitor to sense changes in current flow through a switch that is connects between the input and output of the switching power supply. When the switch runs on, current flows from the input to the output and through a bypass capacitor. The intrinsic series resistance of the bypass capacitor develops a voltage across it as current flows through the capacitor. This voltage is used by a sense circuit to help determine when to shut off the switch. A low-cost regulator develops an output voltage that is divided and compared to a reference to determine if the input voltage is sufficient. If it is not, the power supply is not allowed to operate and the switch is not allowed to turn on.

Abstract: A system and method for reducing non-repeatable positioning errors. Non-repeatable positioning errors caused by the effects stiction and backlash in the mechanical system are reduced by "shaking" or vibrating the positioning system in a controlled manner. After the system input is set to the desired value, the positioning system is "shaken" by inputting a series of offsets that oscillate around the desired location and gradually decrease in amplitude, eventually reaching zero. In a specific embodiment, a lead screw is threaded through a follower nut which is connected to a magnetic tape read/write head. The lead screw is rotated by a mechanical transmission which provides gear reduction from a computer controlled stepper motor. The tape head's non-repeatable positioning error is reduced by alternately stepping the stepper motor in opposite directions a specified number of steps and periodically reducing the specified number of steps until zero is eventually reached.

Abstract: A method of calibrating signal processing circuitry in a magnetic data storage device. The method ensures that an adequate signal-to-noise ratio is achieved when reading a head-position calibration signal. First, discrimination thresholds are set to an initial low value. Then, with wide bandwidth and stationary media, amplifier gain is calibrated by adjusting gain to make the amplitude of amplified background noise equal to the initial threshold value. Finally, bandwidth is reduced and the discrimination thresholds are raised to a final value. The final threshold value ensures that a signal must exceed a predetermined signal-to-noise ratio before the signal is accepted as being valid.

Abstract: A small toroidal inductor is mounted by inserting a high valued resistor or a ceramic coil form into the central hole of the toroid. The fine leads of the inductor are then soldered to the much stiffer leads of the part that has been inserted. These stiffer leads may be bent in any desired way, and will hold their shape. This makes insertion easier and is strong enough to withstand the necessary amounts of shock and vibration. The toroid may be glued or otherwise affixed with an adhesive to the resistor or coil form.

Abstract: A voltage regulator for an anode voltage supply in a CRT powered by a deflection flyback pulse generator includes a voltage sensing network for providing a feedback signal to a summing amplifier. A pulse sensing network which may be a capacitive divider is connected between the output of the flyback pulse generator and the input to the summing amplifier. The resultant output of the summing amplifier is the flyback pulse level shifted with respect to a DC level which is applied to a MOSFET switch to turn it on whenever the flyback pulse goes above the MOSFET's threshold. The output of the MOSFET switches current through a shunt capacitor coupled to the output of the deflection flyback pulse generator for altering its capacitance thereby regulating the height of the flyback pulses, and thus regulating the anode voltage supply.

Abstract: A degaussing system for a CRT includes a voltage source, which is enabled by power-up of the CRT, coupled to a tank circuit including a degaussing coil and a capacitor. A voltage sensing network connected in parallel with the tank circuit senses the voltage across the capacitor and when that voltage rises to a predetermined threshold, and actuating signal is provided which turns on a latching switch circuit which enables a switch connecting the tank circuit to ground. This allows it to oscillate, taking the metal components of the CRT through a decreasing series of hysteresis loops as the oscillation decays. The latching switch circuit maintains the switch in an on position until power-down of the CRT, thus maintaining all except R1 which aids grid regulation of the components of the degaussing system, in a low voltage state until degaussing becomes necessary once again.

Abstract: A scheme for digitizing a stationary video image is disclosed. The amplitude of a video signal, representing said video image, is sampled at a plurality of points along the time axis and is compared with the count in a counter. If the amplitude equals the count at a particular point on the time axis, the count is stored in a memory in a location corresponding to said particular point. The process is repeated until a count in the counter is stored in said memory in locations corresponding to all of said plurality of points along the time axis of said video signal. If two or more counters are used, each counting from a different initial value, and if two or more corresponding comparators are used to make the above comparison, the time required to digitize said stationary video image may be reduced. Consequently, the time required for the video image to remain stationary is reduced.