Abstract: An apparatus and method enables elements of a phase locked loop (PLL) (300). The PLL 300 includes a plurality of elements (202, 203, 204, 205). Each element produces an output signal (207, 208, 209, 116 or 117). Each element has a response time (t3−t2) defined by the difference in time between a first time (t2) at which the element is enabled and a second time (t3), occurring after the first time (t2), at which the output signal of the element reaches a steady state condition. A voltage controlled oscillator (204) of the plurality of elements, having a first response time (t3−t2) is enabled at the first time (t2) responsive to a first control signal (302). A loop divider (205) of the plurality of elements, having a second response time less than the first response time (t3−t2), is enabled responsive to the first response time (t3−t2) and a second control signal (303). The present invention advantageously provides fast lock time for the PLL (300).

Abstract: An error suppressing circuit (301) and method therefor for a phase locked loop (PLL) (300). According to one embodiment of the present invention, a transient condition, for example, a bandwidth switch, in the PLL (300) is detected. The PLL (300) is opened for a period of time (509) responsive to detecting the transient condition. The phase of a reference frequency signal (115) and the phase of a output frequency signal (116 or 117) are synchronized after a lapse of the period of time (509). The PLL (300) is closed responsive to the phase of the reference frequency signal (115) and the phase of the output frequency signal (116 or 117) being synchronized. The present envention advantageously reduces the length of time it takes for the PLL (300) to correct for the phase and frequency error generated by the transient condition, and is capable of operating with various types of PLLs.

Abstract: In a phase locked loop (PLL) (308), an edge proximity detector (302) identifies a phase error, indicative of a difference between a phase of a reference frequency signal (115) and a phase of an output frequency signal (116 or 117), as either desirable or undesirable. When the phase error is identified as desirable, a counter (301) determines a rate of change of the phase error over a first predetermined time period (412) to provide an indication of frequency error (306) between the frequency of the reference frequency signal (206) and the frequency of the output frequency signal (116 or 117); and a loop bandwidth adjuster (310) controls a transition between a first and a second loop bandwidth state of the PLL (308) responsive to the indication of the frequency error (306). When the phase error is identified as undesirable, the PLL (308) operates in the second loop bandwidth state. The present invention advantageously provides an accurate determination of when to vary the loop bandwidth of the PLL (308).