Abstract: An electronic device for data processing is disclosed having a CPU (3), a Closely Coupled Memory (5), an external memory system (8), and a first clock unit (1) and second clock unit (9) for receiving a main clock signal (2) and converting the main clock signal (2) into a first clock signal (6) for at least the Central Processing Unit (3) and Closely Coupled Memory (5) and a second clock signal (10) for the external memory (8). The first clock signal has a first clock frequency and the second clock signal has a second clock frequency being higher than said first clock frequency and wherein the device is configured to switch per time unit the external memory for an active period Tactive in an active state and for a standby period Tstandby in a standby state to retrieve a predetermined amount of data from the external memory per time unit.

Abstract: A power reduction method for a first communication device that can communicate with a second communication device in a synchronized fashion. The first communication device has an electronic module and the method includes generating a communication device shut down signal by the electronic module in order to shut down the communication device apart from the electronic module at a first moment in time, generating a communication device wake-up signal by the electronic module in order to switch on and start booting of the communication device at a second moment in time after the first moment in time, and generating a communication device synchronization signal by the electronic module in order to allow the communication device to restart communicating with the second communication device in the synchronized fashion at a third moment in time after the second moment in time.

Abstract: A method and system for emulating a byte-wise programmable memory in a sector-wise erasable memory, where emulating a byte-wise programmable memory in a sector-wise erasable memory is based on dividing the sector-wise erasable memory in a plurality of sectors, dividing each of the sectors into several memory locations suitable to store containers, with each container having a header and a payload portion, and storing a data value relating to an application in the payload portion of one of the containers and header information identifying the application in the header in an available container. The containers can be block containers, and the data portion can have two or more payload values. The storing action can be performed in such a way that the two or more payload values in the payload portion together uniquely represent the data value.

Abstract: A method and system for emulating a byte-wise programmable memory in a sector-wise erasable memory, where emulating a byte-wise programmable memory in a sector-wise erasable memory is based on dividing the sector-wise erasable memory in a plurality of sectors, dividing each of the sectors into several memory locations suitable to store containers, with each container having a header and a payload portion, and storing a data value relating to an application in the payload portion of one of the containers and header information identifying the application in the header in an available container. The containers can be block containers, and the data portion can have two or more payload values. The storing action can be performed in such a way that the two or more payload values in the payload portion together uniquely represent the data value.

Abstract: An electronic device for data processing is disclosed having a CPU (3), a Closely Coupled Memory (5), an external memory system (8), and a first clock unit (1) and second clock unit (9) for receiving a main clock signal (2) and converting the main clock signal (2) into a first clock signal (6) for at least the Central Processing Unit (3) and Closely Coupled Memory (5) and a second clock signal (10) for the external memory (8). The first clock signal has a first clock frequency and the second clock signal has a second clock frequency being higher than said first clock frequency and wherein the device is configured to switch per time unit the external memory for an active period Tactive in an active state and for a standby period Tstandby in a standby state to retrieve a predetermined amount of data from the external memory per time unit.

Abstract: A power reduction method for a first communication device that can communicate with a second communication device in a synchronized fashion. The first communication device has an electronic module and the method includes generating a communication device shut down signal by the electronic module in order to shut down the communication device apart from the electronic module at a first moment in time, generating a communication device wake-up signal by the electronic module in order to switch on and start booting of the communication device at a second moment in time after the first moment in time, and generating a communication device synchronization signal by the electronic module in order to allow the communication device to restart communicating with the second communication device in the synchronized fashion at a third moment in time after the second moment in time.