Abstract: A digital data processor integrated circuit (1) includes a plurality of functionally identical first processor elements (6A) and a second processor element (5). The first processor elements are bidirectionally coupled to a first cache (12) via a crossbar switch matrix (8). The second processor element is coupled to a second cache (11). Each of the first cache and the second cache contain a two-way, set-associative cache memory that uses a least-recently-used (LRU) replacement algorithm and that operates with a use-as-fill mode to minimize a number of wait states said processor elements need experience before continuing execution after a cache-miss. An operation of each of the first processor elements and an operation of the second processor element are locked together during an execution of a single instruction read from the second cache.

Abstract: A digital data processor integrated circuit (1) includes a plurality of functionally identical first processor elements (6A) and a second processor element (5). The first processor elements are bidirectionally coupled to a first cache (12) via a crossbar switch matrix (8). The second processor element is coupled to a second cache (11). Each of the first cache and the second cache contain a two-way, set-associative cache memory that uses a least-recently-used (LRU) replacement algorithm and that operates with a use-as-fill mode to minimize a number of wait states said processor elements need experience before continuing execution after a cache-miss. An operation of each of the first processor elements and an operation of the second processor element are locked together during an execution of a single instruction read from the second cache.

Abstract: The Parallel DSP Chip has a general purpose, reduced instruction set for parallel digital signal processing. The following pertains to the preferred embodiment. Most instruction words are 32 bits long and execute at the rate of one per clock cycle. Each instruction word is executed by a single pipelined instruction unit that controls the operation of four, 16-bit vector processors in parallel with one group of bits, and the operation of a 24-bit scalar processor with another group of bits. Thus five instructions are typically executed for every instruction word as a result of the parallel architecture. A single, linear, 16 MB, memory address space is used, simplifying program development. The storage of 8- and 16-bit operands for use by the vector processors is supported to maximize memory utilization.

Abstract: The Parallel DSP Chip has a general purpose, reduced instruction set for parallel digital signal processing. The following pertains to the preferred embodiment. Most instruction words are 32 bits long and execute at the rate of one per clock cycle. Each instruction word is executed by a single, pipelined instruction unit that controls the operation of four, 16-bit vector processors in parallel with one group of bits, and the operation of a 24-bit scalar processor with another group of bits. Thus five instructions are typically executed for every instruction word as a result of the parallel architecture. A single, linear, 16 MB, memory address space is used, simplifying program development. The storage of 8- and 16-bit operands for use by the vector processors is supported to maximize memory utilization.

Abstract: A new form of rotating media disk drive is described. Data storage densities of many gigabits per square inch can be obtained at low cost. Data is stored in localized regions of electric charge that are stored within a thin dielectric layer that is coated upon both sides of an electrically conductive platter, rather than in magnetic domains that are stored in thin magnetizable films that are coated upon both sides of platters. Data is stored three-dimensionally, in electric dipoles whose axes are perpendicular to the plane of the platters, rather than in magnetic dipoles that lie along the surface of a platter. Data is read and written via ungated field emitter tips rather than with transformers and magnetically sensitive elements. The read/write head is built from the read/write head chip that contains field emitter tips and other elements.

Abstract: A method for manufacturing ultra high resolution images, especially transmissive images, is described that is capable of fabricating images where each pixture element (pixel) has an intrinsic gray-scale, the gray-scale has a wide dynamic range, there are no voids between pixels, fabrication is not limited by the wavelength of light, and the pixels can be so tiny that their appearance is diffraction-limited. As a result, life-size images of cytology specimens can be fabricated with sufficient spatial and shading detail to show the details of the cell nuclei, and high-density, non-volatile, optical memory devices can be made.

Abstract: A method for manufacturing ultra high resolution images, especially transmissive images, is described that is capable of fabricating images where each pixture element (pixel) has an intrinsic gray-scale, the gray-scale has a wide dynamic range, there are no voids between pixels, fabrication is not limited by the wavelength of light, and the pixels can be so tiny that their appearance is diffraction-limited. As a result, life-size images of cytology specimens can be fabricated with sufficient spatial and shading detail to show the details of the cell nuclei, and high-density, non-volatile, optical memory devices can be made.

Abstract: A programmable signal generating apparatus and method are provided such as for creating a continuous SONET signal. The apparatus preferably comprises a DRAM, a memory address register, a loop counter, an address stack, an instruction decoder, and a SONET data output interface. The DRAM stores a plurality of words at a respective plurality of memory locations. Each word is preferably comprised of three bytes of SONET data and a command byte. One or more command bytes specify a command, and a plurality of commands are decoded by the decoder to generate a plurality of program sequences. The program sequences cause the SONET data bytes which are part of the data words to be generated into continuous SONET frames. The SONET data bytes do not act as typical data operands in that they have no effect upon program operation, but are simply used to generate a SONET data stream.

Abstract: Method and apparatus including a system of integrated ciruit devices for executing matrix operations of the form [A] operated upon by [B] equals [C], where [A], [B] and [C] are each a matrix having a plurality of elements expressed in either unsigned or in two's complement format. The system includes at least one first array of data storage means organized as (j) physical rows and (k) physical columns of bits for providing storage for one bit of each of a plurality of elements of a row vectors of the matrix [A], an individual one of the (j) rows having bits of the same binary weight. The system further includes at least one second array of data storage means organized as (m) physical rows and (n) physical columns of bits, an individual one of the (m) rows storing a same binary weight bit or each of a plurality of elements of a column vector of the matrix [B].

Abstract: A cellular array having a plurality of processor cells disposed on a chip and interconnected by an internal bus includes data bus couplers for bidirectionally coupling to one or more external buses. The data bus couplers selectively couple buses having multiple logic levels. The number of logic levels on the coupled buses may differ. The internal bus may comprise a plurality of parallel data lines each having two-level logic such as binary data, whereas the external buses may have four-level logic represented by four voltage levels. Each data bus coupler has two-bit A/D and D/A converters parallelly connected to selectively convert two bits of two-level logic data to multiple level data and vice versa. The data bus coupler also has a logic level selector circuit using bidirectional gates for selective operation between buses having similar or dissimilar logic levels.

Abstract: In an array of processing cells arranged as a single instruction multiple data processor, each processing cell contains logic which enables the cell to determine individually whether it will perform an arithmetic or logic operation or be in an idle condition. This cell-level logic includes a control register whose contents determine the operating or idle condition of the cell, and also includes PUSH/POP/COMPLEMENT stack mechanisms to represent multiple complex levels of conditions, and mechanisms to load the results of a cell-level test or arithmetic instruction into the control register, providing data-dependent control at the cell level.

Abstract: In a cellular array including a matrixed array of processing elements, the processing elements are controlled by software to overcome manufacturing defects, to cooperate together to form words of varying size and to replace cells that become defective during the lifetime of the processor. These cells communicate with memory external to the chip via a time division multiplex bus. The bus is 32-bits wide and each cell is connected to both the upper half and the lower half of the bus. Configuration bits that are loaded into a cell cause communication over the top half or the bottom half of the bus according to the significance of the bits placed in the cells. Words between 16-bits and 246-bits in length may be formed in a case where 20 such cells are implemented on a single chip with four of the cells being deemed to be spare parts. For simplicity, typical word sizes would be 2n.times.16 bits although in principle any multiple of 16-bits may be obtained.

Abstract: In a cellular array processor at least two of the plurality of processors in a row cooperate together as an address generator so that large amounts of memory external to the array chip may be addressed and in addition so that an address . may be generated onboard for use by the DRAM memory associated with each processor. Based on this structure, a memory with an internal organization that is 256-bits wide may be connected to 16 16-bit processors which would require 256 bits of data. In so doing, a vast number of pins are saved, that is 256 bits of data out of the memory and 256 bits of data into the processing cells by combining the processing cells and memory on the same chip. It is significant that exactly one design of a processing cell may provide both a data processing element and an address processing element. In this way, these cells are interchangeable to maximize the yield and reliability of the device.

Abstract: A processor cell that may be integrated with a multiplicity of dynamically reconfigurable 16-bit slices to enable and disable arbitrary collections of processing elements under software control according to the data being operating upon is provided. The structure allows a collection of word sizes to be defined and then for certain processing elements to be enabled or disabled according to the data that they are operating upon. A slave mechanism is described wherein for words comprised of a multiplicity of slices the most significant slice is in control and the other slices are slaved or forced to go along with the operation of the most significant slice. This slaving is obtained automatically without the necessity to explicitly coordinate the operation of the multiplicity of slices cooperated together to form a word. The cell includes a Find and Lose operation wherein a scaler control means selects one from a multiplicity of processors satisfying some condition.

Abstract: A cellular array processor chip potentially having an unknown number of defects randomly located thereon includes a machine readable record of each defect location, integrated thereon. The record can be a PROM that is programmed at, or after, the end of manufacturing testing.

Abstract: A multiport memory includes first and second signal lines. Each signal line can simultaneously and independently access a particular address during a read memory portion of a clock pulse whereas both signal lines are used to write data to one address during another portion of the clock pulse.

Abstract: A processor apparatus which is capable of performing floating point arithmetic. The processor apparatus includes a plurality of individual processing cells which are interconnected from left to right in a chain so that any of the processor cells can operate to receive a bit of any slice in a digital word. Each cell includes a memory which essentially is coupled via a multiplexer to an arithmetic logic unit, a controllable multiplier quotient store, a controllable loop path, and controllable status path device. Each of these devices are under control of a control mechanism which is included in the cell, and therefore each path can be connected to any other path via various multiplexers utilized in the circuitry. Essentially, each cell includes a multiport RAM, programmable logic arrays which implement the control logic plus path logic which provides the communication between neighboring cells.

Abstract: A cellular array processor chip includes a common bus communicating with the individual cells thereof. The common bus can be monitored during chip testing to detect the presence, or absence, of a defective cell. Each cell can be inactivated with respect to the common bus. During testing if the presence of a defective cell is determined to exist each cell is individually tested until a defective cell is located. That cell is inactivated and the chip testing is resumed until all defective cells are located and inactivated.

Abstract: An array reconfiguration apparatus is employed in large integrated circuits and large systems. The apparatus makes use of spare wires and/or computation elements which are incorporated in the array. The apparatus uses spare wires in place of defective wires and/or the apparatus uses spare computation elements in place of defective computation elements so that an operational system may be created in spite of the occurrence of numerous manufacturing or lifetime faults. The excess wires are utilized as data input and output lines and as such each data line is associated with a bidirectional buffer/receiver (B/R). The bidirectional B/R's are capable of transmitting data in either direction as from an input terminal to an output terminal or vice versa. Each data line is connected to a bidirectional multiplexing device which has a control input. Control logic means has dynamically stored therein the assignment of each significant wire and each computation element.

Abstract: An associative processor array including M rows and N columns of identical processing cells with each cell connected horizontally to its left and right to a neighboring cell. Each cell includes a memory for storing control and data information with the output of the memory coupled to an arithmetic logic unit (ALU) and with the output of the ALU coupled to register means associated with each cell. The entire array formed by the individual cells is capable of performing arithmetic operations on digital words where each word consists of a plurality of bits and a given number of slices. Pursuant to this invention the cells are coupled together in a row via five data paths wherein a first path is operative to move a bit from left to right or from right to left and which first data path is coupled to the memory means in the cells. The second data path is coupled to the ALU's and operative to propagate the arithmetic carry from the ALU of any of the cells unidirectionally to another cell in the same row.