Abstract: A method and apparatus is disclosed for temporarily deferring transmission of frames to a destination in a data switch. When a request for transmission of a frame to the destination port is received, the congestion status of that destination is determined. If the destination is congested, the frame is stored in a deferred queue. When the status of a destination changes from congested to non-congested, the deferred queue is examined to see if any deferred frames can now be forwarded to their destination. While examining the deferred queue, incoming frames are placed on a backup queue. When the deferred queue is fully analyzed, the backup queue is emptied by either sending those frames to their destination or storing the frames in the deferred queue. While examining the deferred queue, the congested states of the destinations are not allowed to change from congested to non-congested.

Abstract: A method and apparatus is disclosed for temporarily deferring transmission of frames to a destination in a data switch. When a request for transmission of a frame to the destination port is received, the congestion status of that destination is determined. If the destination is congested, the frame is stored in a deferred queue. When the status of a destination changes from congested to non-congested, the deferred queue is examined to see if any deferred frames can now be forwarded to their destination. While examining the deferred queue, incoming frames are placed on a backup queue. When the deferred queue is fully analyzed, the backup queue is emptied by either sending those frames to their destination or storing the frames in the deferred queue. While examining the deferred queue, the congested states of the destinations are not allowed to change from congested to non-congested.

Abstract: A method and apparatus is disclosed for temporarily deferring transmission of frames to a destination in a data switch. When a request for transmission of a frame to the destination port is received, the congestion status of that destination is determined. If the destination is congested, the frame is stored in a deferred queue. When the status of a destination changes from congested to non-congested, the deferred queue is examined to see if any deferred frames can now be forwarded to their destination. While examining the deferred queue, incoming frames are placed on a backup queue. When the deferred queue is fully analyzed, the backup queue is emptied by either sending those frames to their destination or storing the frames in the deferred queue. While examining the deferred queue, the congested states of the destinations are not allowed to change from congested to non-congested.

Abstract: A Fiber Channel switch is presented that tracks the congestion status of destination ports in an XOFF mask at each input. A mapping is maintained between virtual channels on an ISL and the destination ports to allow changes in the XOFF mask to trigger a primitive to an upstream port that provides virtual channel flow control. The XOFF mask is also used to avoid sending frames to a congested port. Instead, these frames are stored on a single deferred queue and later processed in a manner designed to maintain frame ordering. A routing system is provided that applies multiple routing rules in parallel to perform line speed routing. The preferred switch fabric is cell based, with techniques used to manage path maintenance for variable length frames and to adapt to varying transmission rates in the system. Finally, the switch allows data and microprocessor communication to share the same crossbar network.

Abstract: A method and apparatus for temporarily deferring transmission of packets/frames to a destination port in a buffered switch is disclosed. When a request for transmission of at least one packet/frame to the destination port is received, it is determined whether the destination port is available to receive the at least one packet/frame. The transmission of the at least one packet/frame is deferred when the destination port is not available to receive the at least one packet/frame. The packet/frame identifier and memory location for each deferred packet/frame is stored in a deferred queue and the process then repeats for the next packet/frame. Periodically, the apparatus attempts to transmit the packets/frames in the deferred queue to their respective destination ports.

Abstract: A method and apparatus that recognizes a portion of an address that would be unrecognizable to an intended associated switch or device and manipulates the portion of the address to make it recognizable. The apparatus and method manipulates a discontinuous address to provide the appearance to the associated device, switch or peripheral, that the address is continuous. This provides additional address capacity such that a new address is created within the switch itself for routing data within the switch. All or a portion of the switches in network are preassigned a chassis address, and each chassis also has a specific switch address that is different from the preassigned chassis address. An address adaptor provides translation of addresses and mapping within a switch so that in the event of a port failure, affected frames can be redirected from the failed port by employing the described translation and mapping operations.

Abstract: A Fiber Channel switch is presented that tracks the congestion status of destination ports in an XOFF mask at each input. A mapping is maintained between virtual channels on an ISL and the destination ports to allow changes in the XOFF mask to trigger a primitive to an upstream port that provides virtual channel flow control. The XOFF mask is also used to avoid sending frames to a congested port. Instead, these frames are stored on a single deferred queue and later processed in a manner designed to maintain frame ordering. A routing system is provided that applies multiple routing rules in parallel to perform line speed routing. The preferred switch fabric is cell based, with techniques used to manage path maintenance for variable length frames and to adapt to varying transmission rates in the system. Finally, the switch allows data and microprocessor communication to share the same crossbar network.

Abstract: A method and apparatus for temporarily deferring transmission of packets/frames to a destination port in a buffered switch is disclosed. When a request for transmission of at least one packet/frame to the destination port is received, it is determined whether the destination port is available to receive the at least one packet/frame. The transmission of the at least one packet/frame is deferred when the destination port is not available to receive the at least one packet/frame. The packet/frame identifier and memory location for each deferred packet/frame is stored in a deferred queue and the process then repeats for the next packet/frame. Periodically, the apparatus attempts to transmit the packets/frames in the deferred queue to their respective destination ports.

Abstract: A multiple arbitration circuit capable of simultaneously arbitrating multiple paths from at least one source port to at least one destination port through a switch. The circuit comprises a crosspoint unit, and a multiple arbitration unit. The multiple arbitration unit comprises a request decoder, a prioritizer, a crosspoint select encoder and an acknowledge OR. The circuit operates such that if a source port is requesting a destination port that no other source port is requesting, then said requested destination port can be arbitrated simultaneously with requests by other source ports for other destination ports.

Abstract: A method and apparatus that recognizes a portion of an address that would be unrecognizable to an intended associated switch or device and manipulates the portion of the address to make it recognizable. The apparatus and method manipulates a discontinuous address to provide the appearance to the associated device, switch or peripheral, that the address is continuous. This provides additional address capacity such that a new address is created within the switch itself for routing data within the switch. All or a portion of the switches in network are preassigned a chassis address, and each chassis also has a specific switch address that is different from the preassigned chassis address. An address adaptor provides translation of addresses and mapping within a switch so that in the event of a port failure, affected frames can be redirected from the failed port by employing the described translation and mapping operations.

Abstract: A clock compensation circuit includes a clock tree; a reference clock; a phase detector for detecting relative phase information of the tree clock and the reference clock; a controller, coupled to said phase detector, for determining and controlling the amount of delay necessary to shift the output of the clock tree in phase with the reference clock; and a programmable delay logic coupled to said controller. The programmable delay logic comprises a string of delay elements that selectively participate in a delay string for shifting the tree clock in phase with the reference clock.

Abstract: A clock compensation circuit includes a clock tree; a reference clock; a phase detector for detecting relative phase information of the tree clock and the reference clock; a controller, coupled to said phase detector, for determining and controlling the amount of delay necessary to shift the output of the clock tree in phase with the reference clock; and a programmable delay logic coupled to said controller. The programmable delay logic comprises a string of delay elements that selectively participate in a delay string for shifting the tree clock in phase with the reference clock.

Abstract: There is provided a dynamic switch organization for error correction of a data path. The dynamic switch organization includes a data path for transmitting data information and control information and a crosspoint switch fabric having a plurality of inputs and a plurality of outputs along the data path. The crosspoint switch fabric has an arbitration bus and crosspoint switch boards coupled to the arbitration bus such that the boards are synchronized to process data in parallel. The crosspoint switch fabric also includes a control entity for directing data from one of the inputs to a particular one of the outputs, and the data includes data bits and check bits. The control entity is distributed among the crosspoint switch boards such that each board includes a portion of the control entity.

Abstract: A FIFO memory eliminates the delay associated with selecting memory locations during a read and write operation and prevents data intended to be saved from changing during the write operation. The FIFO memory includes a shift register having a plurality of memory locations, data input and data output terminals coupled to the memory, a first memory location coupled to the data output terminal that is immediately output enabled in response to a read operation, and a single pointer arrangement coupled to the memory locations for selectively saving data contents in successive memory locations coincidentally with the occurrence of successive write operations.