Abstract: A digital data processing system with a central processor for responding to diverse instructions including instructions for calling subroutines. When the central processor executes a calling instruction, the central processor saves information corresponding to the operating environment for the calling routine and then utilizes corresponding information in the subroutine to establish the operating environment for the subroutine. A common return instruction at the completion of each subroutine causes the central processor to retrieve the saved operating information thereby to reestablish the operating environment for the calling routine.

Abstract: A digital data processing system with a central processor for responding to diverse instructions characterized by having variable length. Each instruction includes an operation code. Certain instructions also include one or more operand specifiers. Each operand specifier can comprise one or more data bytes. Each instruction passes to an instruction buffer. Control circuitry in the central processor decodes the operation code and, in succession, each operand specifier byte. The operand specifiers and information derived from the operation code concerning each operand specifier are combined to obtain the address from which the operand is to be retrieved or to which an operand is to be transferred. Central processor response to an instruction for adding two addends located in first and second storage locations and storing the sum in a third location and instructions for calling a subroutine and returning from the subroutine to the calling routine are disclosed.

Abstract: A digital data processing system with a central processor for responding to diverse instructions characterized by having variable length. Each instruction includes an operation code. Certain instructions also include one or more operand specifiers. Each operand specifier can comprise one or more data bytes. Each instruction passes to an instruction buffer. Control circuitry in the central processor decodes the operation code and, in succession, each operand specifier byte. The operand specifiers and information derived from the operation code concerning each operand specifier are combined to obtain the address from which the operand is to be retrieved or to which an operand is to be transferred. Central processor response to an instruction for adding two addends located in first and second storage locations and storing the sum in a third location and instructions for calling a subroutine and returning from the subroutine to the calling routine are disclosed.

Abstract: A digital data processing system with a central processor for responding to diverse instructions characterized by having variable length. Each instruction includes an operation code. Certain instructions also include one or more operand specifiers. Each operand specifier can comprise one or more data bytes. Each instruction passes to an instruction buffer. Control circuitry in the central processor decodes the operation code and, in succession, each operand specifier byte. The operand specifiers and information derived from the operation code concerning each operand specifier are combined to obtain the address from which the operand is to be retrieved or to which an operand is to be transferred. Central processor response to an instruction for adding two addends located in first and second storage locations and storing the sum in a third location and instructions for calling a subroutine and returning from the subroutine to the calling routine are disclosed.