Abstract: A low electrical and thermal resistance FinFET device includes a semiconductor body, a fin body on the substrate wafer, an isolation structure forming a fin connecting region, a gate dielectric on the fin body extending above the isolation structure, a FinFET gate electrode on the gate dielectric, a heavily-doped buried layer in the semiconductor body extending under said fin, and a vertical conductive region extending from the semiconductor body surface to the heavily-doped buried layer. Additionally, a fin body-to-buried layer implanted region disposed in the fin connecting region provides a low electrical and thermal resistance shunt from the fin body to the heavily-doped buried layer.

Abstract: A low electrical and thermal resistance FinFET device includes a semiconductor body, a fin body on the substrate wafer, an isolation structure forming a fin connecting region, a gate dielectric on the fin body extending above the isolation structure, a FinFET gate electrode on the gate dielectric, a heavily-doped buried layer in the semiconductor body extending under said fin, and a vertical conductive region extending from the semiconductor body surface to the heavily-doped buried layer. Additionally, a fin body-to-buried layer implanted region disposed in the fin connecting region provides a low electrical and thermal resistance shunt from the fin body to the heavily-doped buried layer.

Abstract: A low electrical and thermal resistance FinFET device includes a semiconductor body, a fin body on the substrate wafer, an isolation structure forming a fin connecting region, a gate dielectric on the fin body extending above the isolation structure, a FinFET gate electrode on the gate dielectric, a heavily-doped buried layer in the semiconductor body extending under said fin, and a vertical conductive region extending from the semiconductor body surface to the heavily-doped buried layer. Additionally, a fin body-to-buried layer implanted region disposed in the fin connecting region provides a low electrical and thermal resistance shunt from the fin body to the heavily-doped buried layer.

Abstract: Embodiments described herein provide a chip, comprising a first device on a substrate and a second device on the substrate. The chip further comprises a heat distribution structure in thermal proximity to the first device and the second device, wherein the heat distribution structure is thermally isolated and reduces a thermal gradient between the first device and the second device.

Abstract: An isolated epitaxial modulation device comprises a substrate; a barrier structure formed on the substrate; an isolated epitaxial region formed above the substrate and electrically isolated from the substrate by the barrier structure; a semiconductor device, the semiconductor device located in the isolated epitaxial region; and a modulation network formed on the substrate and electrically coupled to the semiconductor device. The device also comprises a bond pad and a ground pad. The isolated epitaxial region is electrically coupled to at least one of the bond pad and the ground pad. The semiconductor device and the epitaxial modulation network are configured to modulate an input voltage.

Abstract: An isolated epitaxial modulation device comprises a substrate; a barrier structure formed on the substrate; an isolated epitaxial region formed above the substrate and electrically isolated from the substrate by the barrier structure; a semiconductor device, the semiconductor device located in the isolated epitaxial region; and a modulation network formed on the substrate and electrically coupled to the semiconductor device. The device also comprises a bond pad and a ground pad. The isolated epitaxial region is electrically coupled to at least one of the bond pad and the ground pad. The semiconductor device and the epitaxial modulation network are configured to modulate an input voltage.

Abstract: A structure and method of fabricating the structure. The structure including: a dielectric isolation in a semiconductor substrate, the dielectric isolation extending in a direction perpendicular to a top surface of the substrate into the substrate a first distance, the dielectric isolation surrounding a first region and a second region of the substrate, a top surface of the dielectric isolation coplanar with the top surface of the substrate; a dielectric region in the second region of the substrate; the dielectric region extending in the perpendicular direction into the substrate a second distance, the first distance greater than the second distance; and a first device in the first region and a second device in the second region, the first device different from the second device, the dielectric region isolating a first element of the second device from a second element of the second device.

Abstract: A semiconductor structure operation method. The method includes providing a semiconductor structure. The semiconductor structure includes first, second, third, and fourth doped semiconductor regions. The second doped semiconductor region is in direct physical contact with the first and third doped semiconductor regions. The fourth doped semiconductor region is in direct physical contact with the third doped semiconductor region. The first and second doped semiconductor regions are doped with a first doping polarity. The third and fourth doped semiconductor regions are doped with a second doping polarity. The method further includes (i) electrically coupling the first and fourth doped semiconductor regions to a first node and a second node of the semiconductor structure, respectively, and (ii) electrically charging the first and second nodes to first and second electric potentials, respectively. The first electric potential is different from the second electric potential.

Abstract: A semiconductor structure and associated method of formation. The semiconductor structure includes a semiconductor substrate, a first doped transistor region of a first transistor and a first doped Source/Drain portion of a second transistor on the semiconductor substrate, a second gate dielectric layer and a second gate electrode region of the second transistor on the semiconductor substrate, a first gate dielectric layer and a first gate electrode region of the first transistor on the semiconductor substrate, and a second doped transistor region of the first transistor and a second doped Source/Drain portion of the second transistor on the semiconductor substrate. The first and second gate dielectric layers are sandwiched between and electrically insulate the semiconductor substrate from the first and second gate electrode regions, respectively. The first and second gate electrode regions are totally above and totally below, respectively, the top substrate surface.

Abstract: An isolated epitaxial modulation device comprises a substrate; a barrier structure formed on the substrate; an isolated epitaxial region formed above the substrate and electrically isolated from the substrate by the barrier structure; a semiconductor device, the semiconductor device located in the isolated epitaxial region; and a modulation network formed on the substrate and electrically coupled to the semiconductor device. The device also comprises a bond pad and a ground pad. The isolated epitaxial region is electrically coupled to at least one of the bond pad and the ground pad. The semiconductor device and the epitaxial modulation network are configured to modulate an input voltage.

Abstract: A structure for dissipating charge during fabrication of an integrated circuit. The structure includes: a substrate contact in a semiconductor substrate; one or more wiring levels over the substrate; one or more electrically conductive charge dissipation structures extending from a top surface of an uppermost wiring level of the one or more wiring levels through each lower wiring level of the one or more wiring levels to and in electrical contact with the substrate contact; and circuit structures in the substrate and in the one or more wiring layers, the charge dissipation structures not electrically contacting any the circuit structures in any of the one or more wiring levels, the one or more charge dissipation structures dispersed between the circuit structures.

Abstract: A semiconductor structure. The semiconductor structure includes a semiconductor substrate, a first transistor on the semiconductor substrate, and a guard ring on the semiconductor substrate. The semiconductor substrate includes a top substrate surface which defines a reference direction perpendicular to the top substrate surface. The guard ring includes a semiconductor material doped with a doping polarity. A first doping profile of a first doped transistor region of the first transistor in the reference direction and a second doping profile of a first doped guard-ring region of the guard ring in the reference direction are essentially a same doping profile. The guard ring forms a closed loop around the first transistor.

Abstract: A method, including; simultaneously forming a first doped region of an electrostatic discharge protection device and a second doped region of a high-power device by performing a first ion implantation into a semiconductor substrate; and simultaneously forming a third doped region of the electrostatic discharge protection device and a fourth doped region of a first low power device by performing a second ion implantation into the semiconductor substrate, the first ion implantation different from the second ion implantation, the electrostatic discharge device being a different device type from the high-power device and the electrostatic discharge device having a different structure from the high-power device.

Abstract: An electrical structure and method of forming. The electrical structure includes a semiconductor substrate comprising a deep trench, an oxide liner layer is formed over an exterior surface of the deep trench, and a field effect transistor (FET) formed within the semiconductor substrate. The first FET includes a source structure, a drain structure, and a gate structure. The gate structure includes a gate contact connected to a polysilicon fill structure. The polysilicon fill structure is formed over the oxide liner layer and within the deep trench. The polysilicon fill structure is configured to flow current laterally across the polysilicon fill structure such that the current will flow parallel to a top surface of the semiconductor substrate.

Abstract: Embodiments described herein provide a chip, comprising a first device on a substrate and a second device on the substrate. The chip further comprises a heat distribution structure in thermal proximity to the first device and the second device, wherein the heat distribution structure is thermally isolated and reduces a thermal gradient between the first device and the second device.

Abstract: A method of forming complementary metal-oxide-silicon logic field effect transistors, high power transistors and electrostatic discharge protection diodes and/or electrostatic discharge protection shunt transistors on the same integrated circuit chip using ion implantations used to fabricate the field effect transistors and high-power transistor to simultaneously fabricate the electrostatic discharge protection diodes and/or electrostatic discharge protection shunt transistors.

Abstract: Diodes and method of fabricating diodes. A diode includes: an p-type single wall carbon nanotube; an n-type single wall carbon nanotube, the p-type single wall carbon nanotube in physical and electrical contact with the n-type single wall carbon nanotube; and a first metal pad in physical and electrical contact with the p-type single wall carbon nanotube and a second metal pad in physical and electrical contact with the n-type single wall carbon nanotube.

Abstract: A structure and method of fabricating the structure. The structure including: a dielectric isolation in a semiconductor substrate, the dielectric isolation extending in a direction perpendicular to a top surface of the substrate into the substrate a first distance, the dielectric isolation surrounding a first region and a second region of the substrate, a top surface of the dielectric isolation coplanar with the top surface of the substrate; a dielectric region in the second region of the substrate; the dielectric region extending in the perpendicular direction into the substrate a second distance, the first distance greater than the second distance; and a first device in the first region and a second device in the second region, the first device different from the second device, the dielectric region isolating a first element of the second device from a second element of the second device.

Abstract: A structure and method of fabricating the structure. The structure including: a dielectric isolation in a semiconductor substrate, the dielectric isolation extending in a direction perpendicular to a top surface of the substrate into the substrate a first distance, the dielectric isolation surrounding a first region and a second region of the substrate, a top surface of the dielectric isolation coplanar with the top surface of the substrate; a dielectric region in the second region of the substrate; the dielectric region extending in the perpendicular direction into the substrate a second distance, the first distance greater than the second distance; and a first device in the first region and a second device in the second region, the first device different from the second device, the dielectric region isolating a first element of the second device from a second element of the second device.

Abstract: A semiconductor structure operation method. The method includes providing a semiconductor structure. The semiconductor structure includes first, second, third, and fourth doped semiconductor regions. The second doped semiconductor region is in direct physical contact with the first and third doped semiconductor regions. The fourth doped semiconductor region is in direct physical contact with the third doped semiconductor region. The first and second doped semiconductor regions are doped with a first doping polarity. The third and fourth doped semiconductor regions are doped with a second doping polarity. The method further includes (i) electrically coupling the first and fourth doped semiconductor regions to a first node and a second node of the semiconductor structure, respectively, and (ii) electrically charging the first and second nodes to first and second electric potentials, respectively. The first electric potential is different from the second electric potential.