Abstract: An illustrative embodiment provides a computer-implemented process for algorithm complexity identification through inter-procedural data flow analysis receives a call graph to form a set of received nodes in a static analysis framework, identifies a parent node in the set of received nodes to form an identified parent, traverses the call graph from the identified parent node to a node to identify a function within the node to form an identified function. Each identified function is analyzed to form a complexity value in a set of complexity values. Responsive to a determination that node analysis is complete, and responsive to a determination that path analysis is complete, determines whether path analysis for the identified parent is complete. Responsive to a determination that path analysis for the identified parent is complete, sum the complexity values in the set of complexity values for the identified parent and return the complexity value for the identified parent to a requester.

Abstract: An illustrative embodiment provides a computer-implemented process for algorithm complexity identification through inter-procedural data flow analysis receives a call graph to form a set of received nodes in a static analysis framework, identifies a parent node in the set of received nodes to form an identified parent, traverses the call graph from the identified parent node to a node to identify a function within the node to form an identified function. Each identified function is analyzed to form a complexity value in a set of complexity values. Responsive to a determination that node analysis is complete, and responsive to a determination that path analysis is complete, determines whether path analysis for the identified parent is complete. Responsive to a determination that path analysis for the identified parent is complete, sum the complexity values in the set of complexity values for the identified parent and return the complexity value for the identified parent to a requester.

Abstract: A system and method are described for bit rate detection in a serial data communication system, the system employing a data rate prompt of a pair of opposite value data bits which follow a series of idle bits. In a first embodiment a receiving port employs a clocked delay element and a set of data clock rates, each data clock rate being a multiple N of one of a set of established bit transmission rates, ranging from a highest expected bit rate to a lowest expected bit rate. The bit rate detection method comprises: clocking the delay element at the highest data clock rate, upon the sensing of one of the opposite value data rate prompt bits at the delay element, to step the value of the sensed bit into the delay element. After a predetermined number of data clock pulses have stepped the value of the sensed bit into the delay element, the system compares the bit value at an input to the delay element and the bit value in a bit position of the delay element.

Abstract: In an excimer laser system with wavelength bandwidth narrowing, a feedback loop for monitoring and correcting the tuning of the laser employs a wavelength calibration device in the form of a gas with an absorption peak at the desired narrow wavelength. A portion of the laser output received through the gas provides the information for generating the correction signal.