Abstract: A method of transferring data between a first electrical component (16) and a second electrical component (18), which are both coupled to a common oscillator (62) that oscillates at a first frequency, the first electrical component (16) generating a first bit stream having a second frequency that is a fraction of the first frequency and having a first number of bits, generating an indicator signal having a third frequency that is a fraction of the first frequency and that is indicative of a type of data represented by the first bit stream, and coupling the first bit stream and the indicator signal to the second electrical component. The second electrical component (18) sampling the first bit stream and the indicator signal at a fourth frequency that is substantially identical to the second frequency, thereby recovering the first bit stream generated by the first electrical component (16) and determining the type of data contained in the first bit stream.

Abstract: An apparatus (200) for securing electronic information (205) includes a microcontroller (202) and an external memory (204) coupled thereto. The microcontroller (202) comprises a one-time programmable security flag (230) that is programmed when the electronic information (205) is stored in the memory (204). Once programmed, the security flag prevents reprogramming of the memory (204). Additionally, the microcontroller (202) comprises an algorithm (400) that generates electronic authentication information (207) from the electronic information (205). The authentication information (207) is stored in the memory (204) along with the electronic information (205). Upon retrieval from the memory (204) for registration, the electronic information (205) is authenticated by generating new electronic authentication information (508) via the algorithm (400) to compare to the authentication information (207) stored in the memory (204). Such authentication prevents swapping out of the memory (204) to gain system access.

Abstract: An apparatus for discontinuously operating a receiver (302) includes a receive data circuitry (304) and processor circuitry (306). The apparatus and receiver (302) are incorporated in a communication device (104). The receiver (302) receives a communication signal (106) having a plurality of frames (200, 214, 224). Each of the frames has a synchronization field (202, 217, 222) followed by a data field (204, 218, 228). The receive data circuitry (304) synchronizes the communication device (104) with the communication signal (106) received by the receiver (302) according to an initial synchronization field (202). The receive data circuitry (304) decodes the following data field (204). The processor (306) evaluates the decoded data field. If the decoded data field indicates that the receiver (302) is locked, the processor (306) powers off the receiver (302) for the following synchronization fields (222).