Abstract: The present invention provides a method, system and apparatus for providing failsafe detection for a differential receiver. A bus activity signal (11) is activated when receiving a differential data signal of sufficient amplitude to transition through a predetermined threshold. A failsafe signal (620) indicates a low differential voltage condition. A countdown time period commences (85) upon activation of either signal, and a failsafe condition is determined (89) to exist if the failsafe signal is active (87) when the countdown time period expires (86).

Abstract: A driver (300) which meets wide common mode voltage requirements is provided. Output passgates (310) protect sensitive line driver circuitry (305) from extreme bus voltages; enabling/disabling circuits (315, 316) detect fault conditions to ensure the line driver is disabled when needed, and pull-ups (320) assist in line driver start up by preventing negative voltage conditions on the bus driven by the line driver.

Abstract: A circuit that provides a stable predrive to a BiCMOS LVDS output which compensates for supply voltage variations while maintaining a suitably fast signal path. The supply voltage compensation circuit provides an offset to the predrive level shift such that when the supply voltage Vcc rises, the predrive output voltage is lowered in response.

Abstract: A system 500 and method 900 is disclosed for a driver circuit used for high speed data transmission in LVDS transceiver device applications (e.g., LVDS repeaters and PECL/ECL to LVDS converters). The transceivers are intended to receive a low voltage differential input signal and drive an TIA/EIA-644 compliant LVDS signal. The driver circuit operates at speeds up to 1.36 Gbps, making it compatible with the OC-24 signaling rate for optical transmission. To accomplish this, the driver uses a mixed combination of voltage and current mode drive sections in the output circuit. MOS transistors and a current source are used in the current mode switch portion to switch the drive with a constant current at the high speeds, and NPN transistors in the voltage mode output portion provide variable impedance for the output circuit.

Abstract: A circuit that provides a stable predrive to a BiCMOS LVDS output which compensates for supply voltage variations while maintaining a suitably fast signal path. The supply voltage compensation circuit provides an offset to the predrive level shift such that when the supply voltage Vcc rises, the predrive output voltage is lowered in response.

Abstract: The present invention provides a method, system and apparatus for providing failsafe detection for a differential receiver. A bus activity signal (11) is activated when receiving a differential data signal of sufficient amplitude to transition through a predetermined threshold. A failsafe signal (620) indicates a low differential voltage condition. A countdown time period commences (85) upon activation of either signal, and a failsafe condition is determined (89) to exist if the failsafe signal is active (87) when the countdown time period expires (86).

Abstract: The present invention provides improved slew rate control over a varied operating temperature range. A switching device (P1, N1) receives from a predrive circuit (56) a control signal that limits a slew rate of the switching device's output and also varies proportionally to the operating temperature. In this manner, the effect of temperature on the slew rate can be reduced.

Abstract: The output slew rate of a differential transmission line driver (13) can be limited by suitably controlling signal slew rates (52) at the control inputs (neg, pos) of the drive switches (M1-M4) that control current flow through the load impedance (Rload) of the driver.

Abstract: The output slew rate of a differential transmission line driver (13) can be limited by suitably controlling signal slew rates (52) at the control inputs (neg, pos) of the drive switches (M1-M4) that control current flow through the load impedance (Rload) of the driver.

Abstract: A fast voltage differential signaling (LVDS) transceiver (50) having high repeater speeds up to 1.36 GBps, and also meeting the TIA/EIA-644 standard short-to-ground requirements. A mixed voltage-current mode differential driver has a respective control signal (A3) driving each of the drive transistors (Q3). The control signal (A3) is controlled by a transistor (M1) being a function of current through the respective drive transistor (Q3). A current mirror (Q4, Q5, Q6) is used to mirror current conducting through a transistor (Q4) in parallel with the drive transistor (Q3), which mirror current is compared against a current reference (Iref).

Abstract: A low-current oscillator with input buffer hysteresis for increased noise immunity during oscillator start-up. Resistors are switched in and out of the comparator input elements creating offsets in one leg of the comparator at a time.