Abstract: The present disclosure includes a coil protection assembly configured to be incorporated into a piece of sports equipment such as a glove, shin guard, or shoulder pad. The coil protection assembly may include a coil element spiraled to form a plurality of loops. The coil protection assembly may also have a foam layer disposed on the interior surface of the coil element. An outer layer may enclose or encase the coil element and the foam layer with the loops free to move with respect to one another, A strip of liner material may be secured to the outer layer to connect the loop together. The liner material may be an elastic material to allow the loops to move away from each other, yet still retract back to a default position.

Abstract: The present invention relates to methods for self renewal of stem cells. In particular the invention relates to stem cells of increased transplant potential or enhanced self renewal, stem cell cultures derived therefrom and uses of the stem cell cultures for treatment and particularly for transplantation and gene therapy protocols.

Abstract: An integrated circuit chip is fabricated as several circuit modules that are synchronized with a clock signal, by the following steps. Initially, a hardware description language is used to describe a functional behavior for a first module on the chip which generates an intermodule signal, and describe a functional behavior for a second module on the chip which processes the intermodule signal. Thereafter, a slow circuit embodiment of the first module is synthesized with port timing constraints which permit the intermodule signal to be generated in twice the cycle time T.sub.CY of the clock signal, and a slow circuit embodiment of the second module is synthesized with port timing constraints which permit the intermodule signal to be processed in twice the cycle time of the clock. Then, a timing analysis program is run on the slow circuit embodiment of the first and second modules to thereby obtain a first delay .DELTA..sub.1 in which the intermodule signal is actually generated, and obtain a second delay .