Abstract: An analog-to-digital converter (ADC) includes a resistor network for generating multiple reference voltages. The resistor network includes multiple resistors connected in series to form a resistor string. A first portion of the resistors between either one of two end nodes and a central node of the string have substantially equal electrical resistances. A second portion of the resistors are refinements of at least part of the first portion resistors and are arranged further from the central node than the resistors of the first portion. Resistances of the second portion resistors are greater than resistances of the first portion resistors. When an electrical potential is applied between the two end nodes, the multiple reference voltages are produced between adjacent resistors. An ADC is also described including first and second capacitor arrays and a comparator. An apparatus and method are disclosed for generating a binary value corresponding to an analog input voltage.

Abstract: A configuration of sub-comparators for use within an analog to digital conversion circuit is disclosed. A number of the sub-comparators are adapted to receive equalization and power down control signals. In one embodiment, several of the sub-comparators are cascaded together in the analog to digital conversion circuit. An equalization signal and a power down control signal are applied to at least some of the sub-comparators enabling the sub-comparators to attenuate or eliminate offset voltage and environmental noise associated with the signal to be sampled. Furthermore, in accordance with another aspect, the analog to digital conversion circuit includes a latch type differential sub-comparator, which can attenuate or eliminate output levels of the sub-comparators from residing in an unstable input region of the digital converter.

Abstract: An analog-to-digital converter (ADC) includes a resistor network for generating multiple reference voltages. The resistor network includes multiple resistors connected in series to form a resistor string. A first portion of the resistors between either one of two end nodes and a central node of the string have substantially equal electrical resistances. A second portion of the resistors are refinements of at least part of the first portion resistors and are arranged further from the central node than the resistors of the first portion. Resistances of the second portion resistors are greater than resistances of the first portion resistors. When an electrical potential is applied between the two end nodes, the multiple reference voltages are produced between adjacent resistors. An ADC is also described including first and second capacitor arrays and a comparator. An apparatus and method are disclosed for generating a binary value corresponding to an analog input voltage.

Abstract: Automatic alignment methods for a membrane prober are disclosed. Alignment patterns are designed and manufactured on both a membrane prober and a wafer under test. The patterns are properly designed for acquiring a first set of measurement data that provide relative position information when the prober contacts the wafer. A second set of measurement data can be obtained by a controlled move between the prober and the wafer. The relative position including the translation offset and the rotation angle can be computed by the information derived from the two sets of measurement data. The second set of measurement data may also be acquired by having two alignment pattern pairs that are made to contact in a single touch. More accurate aligrnent can be achieved by using more pairs of alignment patterns.