Abstract: A technique to reduce false error detection in microprocessors by tracking instructions neutral to errors. As an instruction is decoded, an anti-pi bit is tagged to the decoded instruction. When a parity error is detected, an instruction queue first checks if the anti-pi bit is set. If the anti-pi bit is set, then instruction is neutral to errors, and the pi bit need not be set. Prefetch, branch predict hint and NOP are types of instructions that are neutral to errors.

Abstract: Log-based hardware recovery. A checkpointed state of a system includes both architectural register values and memory. The checkpoint consists of a copy of the architectural register file values at the time the checkpoint is generated. An ordered log of non-deterministic events is maintained so that the responses can be repeated to simulate a complete checkpoint for error recovery purposes. When a processor detects an error, the processor reloads the state from the last checkpoint and repeats the non-deterministic events from the log.

Abstract: A method and apparatus for a checker instruction in a redundant multithreading environment is described. In one embodiment, when RMT requires, a processor may issue a checker instruction in both a leading thread and a trailing thread. The checker instruction may travel down individual pipelines for each thread independently until it reaches a buffer at the end of each pipeline. Then, prior to committing the checker instruction, the checker instruction looks for its counterpart and does a comparison of the instructions. If the checker instructions match, the checker instructions commit and retires otherwise an error is declared.

Abstract: A computer software product, methods and apparatus for target report generation are provided. In one embodiment, a trigger pattern is derived from at least one target pattern. Locations within a data set containing the trigger pattern are identified and a target report is generated. In another embodiment, a computing apparatus is provided that produces reports by deriving a trigger pattern, identifying locations within a dataset where the trigger patterns exist and generating a report. In a further embodiment, a computer software product is provided that configures an apparatus to generate a target report. This Abstract is provided for the sole purpose of complying with the Abstract requirement rules that allow a reader to quickly ascertain the subject matter of the disclosure contained herein. This Abstract is submitted with the explicit understanding that it will not be used to interpret or to limit the scope or the meaning of the claims.

Abstract: A multithreaded architecture having one or more checker circuits that operate on store operations that send data outside of a sphere of replication. Fault detection mechanisms used to check outputs from the sphere of replication are reused for checkpointing at the conclusion of an execution epoch.

Abstract: A technique to detect errors in a computer system. More particularly, at least one embodiment of the invention relates to using redundant virtual machines and comparison logic to detect errors occurring in input/output (I/O) operations in a computer system.

Abstract: A processor executes corresponding instruction threads as a leading thread and a trailing thread. For a selected instruction, processor state corresponding to the execution of the instruction is saved in a history buffer. This is performed before writing a result from the selected instruction to a destination register. The result from executing the selected instruction in the leading thread is compared to the result from executing the selected instruction in the trailing thread. If the comparison indicates a fault, then restoring the processor state corresponding to a previous instruction. Data from the history buffer is used to perform the restoration.

Abstract: A simultaneous and redundantly threaded, pipelined processor executes the same set of instructions simultaneously as two separate threads to provide fault tolerance. One thread is processed ahead of the other thread so that the instructions in one thread are processed through the processor's pipeline ahead of the corresponding instructions from the other thread. The thread, whose instructions are processed earlier, places its committed stores in a store queue. Subsequently, the second thread places its committed stores in the store queue. A compare circuit periodically scans the store queue for matching store instructions. If otherwise matching store instructions differ in any way (address or data), then a fault has occurred in the processing and the compare circuits initiates fault recovery. If comparison of the two instructions reveals they are identical, the compare circuit allows only a single store instruction to pass to the data cache or the system main memory.

Abstract: A processor is disclosed having a fetch unit that initiating interrupt service routines in redundant, unsynchronized threads. A counter is provided to track the difference between leading and trailing threads in terms of the number of instructions committed by the instruction execution circuitry. When the processor receives an external interrupt signal, the instruction fetch unit stalls the leading thread until the counter indicates that the threads are synchronized, and then simultaneously initiates an interrupt service routine in each of the threads. In a second embodiment similar to the first, the instruction fetch unit does not stall the leading thread, but rather, immediately initiates the interrupt service routine in the leading thread, and copies the difference to an interrupt counter. When the counter reaches zero, the fetch unit initiates the interrupt service routine in the trailing thread.

Abstract: A redundantly threaded processor is disclosed having an Active Load Address Buffer (“ALAB”) that ensures efficient replication of data values retrieved from the data cache. In one embodiment, the processor comprises a data cache, instruction execution circuitry, and an ALAB. The instruction execution circuitry executes instructions in two or more redundant threads. The threads include at least one load instruction that causes the instruction execution circuitry to retrieve data from the data cache. The ALAB includes entries that are associated with data values that a leading thread has retrieved. The entries include a counter field that is incremented when the instruction execution circuitry retrieves the associated data value for the leading thread, and that is decremented with the associated data value is retrieved for the trailing thread. The entries preferably also include an invalidation field which may be set to prevent further incrementing of the counter field.

Abstract: A pipelined, simultaneous and redundantly threaded (“SRT”) processor configured to detect transient faults during program execution by executing instructions in at least two redundant copies of a program thread and wherein misspeculation caused by incorrectly predicting the outcomes of branch instructions in a second program thread is avoided by using the actual outcomes of branch instructions in a first program thread to correctly predict the outcome of branch instructions in the second program thread. The SRT processor comprises a branch predictor for speculating the outcomes of branch instructions in the first program thread and a branch outcome queue for storing the actual outcomes of branch instructions in the first program thread. The processor uses the branch outcome queue and not the branch predictor to predict the outcomes of branch instructions in the second program thread.

Abstract: A processor is disclosed having a fetch unit that initiating interrupt service routines in redundant, unsynchronized threads. A counter is provided to track the difference between leading and trailing threads in terms of the number of instructions committed by the instruction execution circuitry. When the processor receives an external interrupt signal, the instruction fetch unit stalls the leading thread until the counter indicates that the threads are synchronized, and then simultaneously initiates an interrupt service routine in each of the threads. In a second embodiment similar to the first, the instruction fetch unit does not stall the leading thread, but rather, immediately initiates the interrupt service routine in the leading thread, and copies the difference to an interrupt counter. When the counter reaches zero, the fetch unit initiates the interrupt service routine in the trailing thread.

Abstract: A redundantly threaded processor is disclosed having an Active Load Address Buffer (“ALAB”) that ensures efficient replication of data values retrieved from the data cache. In one embodiment, the processor comprises a data cache, instruction execution circuitry, and an ALAB. The instruction execution circuitry executes instructions in two or more redundant threads. The threads include at least one load instruction that causes the instruction execution circuitry to retrieve data from the data cache. The ALAB includes entries that are associated with data values that a leading thread has retrieved. The entries include a counter field that is incremented when the instruction execution circuitry retrieves the associated data value for the leading thread, and that is decremented with the associated data value is retrieved for the trailing thread. The entries preferably also include an invalidation field which may be set to prevent further incrementing of the counter field.

Abstract: A simultaneous and redundantly threaded, pipelined processor executes the same set of instructions simultaneously as two separate threads to provide fault tolerance. One thread is processed ahead of the other thread so that the instructions in one thread are processed through the processor's pipeline ahead of the corresponding instructions from the other thread. The thread, whose instructions are processed earlier, places its committed stores in a store queue. Subsequently, the second thread places its committed stores in the store queue. A compare circuit periodically scans the store queue for matching store instructions. If otherwise matching store instructions differ in any way (address or data), then a fault has occurred in the processing and the compare circuits initiates fault recovery. If comparison of the two instructions reveals they are identical, the compare circuit allows only a single store instruction to pass to the data cache or the system main memory.

Abstract: A device interface for communicating between a processor system and a separate device employs cacheable control registers, both to indicate the receipt of a message and to receive messages to be transmitted. The data structure of the cacheable control registers may be that of a queue, minimizing the need for routine handshaking signals to clear the queue after each message. Communication of queue pointers is minimized by the use of a shadow pointer relied on as long as adequate queue space exists and queue entry valid flags which are interpreted with alternate sense for each cycling through the queue.