Patents by Inventor Steven Kummerl
Steven Kummerl has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11854947Abstract: An integrated circuit (IC) chip can include a die with an interconnect conductively coupled to a leadframe, wherein the leadframe forms a portion of a given surface of the IC chip. The IC chip can also include an encapsulating material molded over the die and the leadframe. The encapsulating material can form another surface of the IC chip. The other surface of the IC chip opposes the given surface of the IC chip. The IC chip can further include a vertical wire extending through the encapsulating material in a direction that is substantially perpendicular to the given surface of the IC chip and the vertical wire protruding through the other surface of the IC chip to form a vertical connector for the IC chip. The vertical connector can be coupled to the interconnect on the die.Type: GrantFiled: October 13, 2020Date of Patent: December 26, 2023Assignee: Texas Instruments IncorporatedInventors: Abram M. Castro, Steven Kummerl
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Publication number: 20210091012Abstract: A floating die package including a cavity formed through sublimation of a sacrificial die encapsulant and sublimation or separation of die attach materials after molding assembly. A pinhole vent in the molding structure is provided as a sublimation path to allow gases to escape, whereby the die or die stack is released from the substrate and suspended in the cavity by the bond wires only.Type: ApplicationFiled: December 8, 2020Publication date: March 25, 2021Inventors: Benjamin Stassen Cook, Steven Kummerl, Kurt Peter Wachtler
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Publication number: 20210028093Abstract: An integrated circuit (IC) chip can include a die with an interconnect conductively coupled to a leadframe, wherein the leadframe forms a portion of a given surface of the IC chip. The IC chip can also include an encapsulating material molded over the die and the leadframe. The encapsulating material can form another surface of the IC chip. The other surface of the IC chip opposes the given surface of the IC chip. The IC chip can further include a vertical wire extending through the encapsulating material in a direction that is substantially perpendicular to the given surface of the IC chip and the vertical wire protruding through the other surface of the IC chip to form a vertical connector for the IC chip. The vertical connector can be coupled to the interconnect on the die.Type: ApplicationFiled: October 13, 2020Publication date: January 28, 2021Inventors: Abram M. Castro, Steven Kummerl
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Patent number: 10887993Abstract: An apparatus includes an electrical device having a surface. The electrical device includes a first surface conductor spaced apart from a second surface conductor on the surface to provide circuit contacts to the device. A first standoff connector is bonded to the first surface conductor. The first standoff connector includes a leg having a proximal end bonded to the first surface conductor. The leg of the first standoff connector extends outwardly from the first surface conductor to a bend that is spaced apart from the surface of the electrical device. A second standoff connector is bonded to the second surface conductor. The second standoff connector includes a leg having a proximal end bonded to the second surface conductor. The leg of the second standoff connector extends outwardly from the second surface conductor to a bend that is spaced apart from the surface of the electrical device.Type: GrantFiled: December 31, 2015Date of Patent: January 5, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventor: Steven Kummerl
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Patent number: 10861796Abstract: A floating die package including a cavity formed through sublimation of a sacrificial die encapsulant and sublimation or separation of die attach materials after molding assembly. A pinhole vent in the molding structure is provided as a sublimation path to allow gases to escape, whereby the die or die stack is released from the substrate and suspended in the cavity by the bond wires only.Type: GrantFiled: August 26, 2016Date of Patent: December 8, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Benjamin Stassen Cook, Steven Kummerl, Kurt Peter Wachtler
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Patent number: 10804185Abstract: An integrated circuit (IC) chip can include a die with an interconnect conductively coupled to a leadframe, wherein the leadframe forms a portion of a given surface of the IC chip. The IC chip can also include an encapsulating material molded over the die and the leadframe. The encapsulating material can form another surface of the IC chip. The other surface of the IC chip opposes the given surface of the IC chip. The IC chip can further include a vertical wire extending through the encapsulating material in a direction that is substantially perpendicular to the given surface of the IC chip and the vertical wire protruding through the other surface of the IC chip to form a vertical connector for the IC chip. The vertical connector can be coupled to the interconnect on the die.Type: GrantFiled: December 31, 2015Date of Patent: October 13, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Abram M. Castro, Steven Kummerl
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Publication number: 20200083147Abstract: A packaged semiconductor device includes an IC die having bump features that are coupled to bond pads flip chip attached to a custom LF. The custom LF includes metal structures including metal leads on at least 2 sides, and printed metal providing a printed LF portion including printed metal traces that connect to and extend inward from at least one of the metal leads over the dielectric support material that are coupled to FC pads configured for receiving the bump features including at least some of the printed metal traces coupled to the bond pads on the IC die. The IC die is flip chip mounted on the printed LF portion so that the bump features are connected to the FC pads.Type: ApplicationFiled: September 6, 2018Publication date: March 12, 2020Inventors: JO BITO, BENJAMIN STASSEN COOK, STEVEN KUMMERL
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Publication number: 20200035833Abstract: A method to improve transistor performance uses a wafer (100) of single-crystalline semiconductor with a first zone (102) of field effect transistors (FETs) and circuitry at the wafer surface, and an infrared (IR) laser with a lens for focusing the IR light to a second depth (112) farther from the wafer surface than the first depth of the first zone. The focused laser beam is moved parallel to the surface across the wafer to cause local multi-photon absorption at the second depth for transforming the single-crystalline semiconductor into a second zone (111) of polycrystalline semiconductor with high density of dislocations. The second zone has a height and lateral extensions, and permanently stresses the single-crystalline bulk semiconductor; the stress increases the majority carrier mobility in the channel of the FETs, improving the transistor performance.Type: ApplicationFiled: October 1, 2019Publication date: January 30, 2020Inventors: Steven Kummerl, Matthew John Sherbin, Saumya Gandhi
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Patent number: 10535594Abstract: A semiconductor device comprises an interposer with extruded feed-through vias and a semiconductor die. The interposers includes a substrate having a plurality of through-vias. A dielectric liner lining said through-vias. A plurality of feed-thru electrically conducting features provided by a plurality of extruded metal wires within said dielectric liner. A semiconductor die attached to said interposer.Type: GrantFiled: January 19, 2016Date of Patent: January 14, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventor: Steven Kummerl
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Patent number: 10431684Abstract: A method to improve transistor performance uses a wafer (100) of single-crystalline semiconductor with a first zone (102) of field effect transistors (FETs) and circuitry at the wafer surface, and an infrared (IR) laser with a lens for focusing the IR light to a second depth (112) farther from the wafer surface than the first depth of the first zone. The focused laser beam is moved parallel to the surface across the wafer to cause local multi-photon absorption at the second depth for transforming the single-crystalline semiconductor into a second zone (111) of polycrystalline semiconductor with high density of dislocations. The second zone has a height and lateral extensions, and permanently stresses the single-crystalline bulk semiconductor; the stress increases the majority carrier mobility in the channel of the FETs, improving the transistor performance.Type: GrantFiled: April 22, 2016Date of Patent: October 1, 2019Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Steven Kummerl, Matthew John Sherbin, Saumya Gandhi
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Publication number: 20180323361Abstract: A circuit board includes an embedded thermoelectric device with hard thermal bonds. A method includes embedding a thermoelectric device in a circuit board and forming hard thermal bonds.Type: ApplicationFiled: July 10, 2018Publication date: November 8, 2018Inventors: Henry L. Edwards, Kenneth J. Maggio, Steven Kummerl, Sreenivasan K. Koduri
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Publication number: 20170330841Abstract: A floating die package including a cavity formed through sublimation of a sacrificial die encapsulant and sublimation or separation of die attach materials after molding assembly. A pinhole vent in the molding structure is provided as a sublimation path to allow gases to escape, whereby the die or die stack is released from the substrate and suspended in the cavity by the bond wires only.Type: ApplicationFiled: August 26, 2016Publication date: November 16, 2017Inventors: Benjamin Stassen Cook, Steven Kummerl, Kurt Peter Wachtler
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Publication number: 20170309748Abstract: A method to improve transistor performance uses a wafer (100) of single-crystalline semiconductor with a first zone (102) of field effect transistors (FETs) and circuitry at the wafer surface, and an infrared (IR) laser with a lens for focusing the IR light to a second depth (112) farther from the wafer surface than the first depth of the first zone. The focused laser beam is moved parallel to the surface across the wafer to cause local multi-photon absorption at the second depth for transforming the single-crystalline semiconductor into a second zone (111) of polycrystalline semiconductor with high density of dislocations. The second zone has a height and lateral extensions, and permanently stresses the single-crystalline bulk semiconductor; the stress increases the majority carrier mobility in the channel of the FETs, improving the transistor performance.Type: ApplicationFiled: April 22, 2016Publication date: October 26, 2017Inventors: Steven Kummerl, Matthew John Sherbin, Saumya Gandhi
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Publication number: 20170196090Abstract: An apparatus includes an electrical device having a surface. The electrical device includes a first surface conductor spaced apart from a second surface conductor on the surface to provide circuit contacts to the device. A first standoff connector is bonded to the first surface conductor. The first standoff connector includes a leg having a proximal end bonded to the first surface conductor. The leg of the first standoff connector extends outwardly from the first surface conductor to a bend that is spaced apart from the surface of the electrical device. A second standoff connector is bonded to the second surface conductor. The second standoff connector includes a leg having a proximal end bonded to the second surface conductor. The leg of the second standoff connector extends outwardly from the second surface conductor to a bend that is spaced apart from the surface of the electrical device.Type: ApplicationFiled: December 31, 2015Publication date: July 6, 2017Inventor: Steven KUMMERL
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Publication number: 20170194233Abstract: An integrated circuit (IC) chip can include a die with an interconnect conductively coupled to a leadframe, wherein the leadframe forms a portion of a given surface of the IC chip. The IC chip can also include an encapsulating material molded over the die and the leadframe. The encapsulating material can form another surface of the IC chip. The other surface of the IC chip opposes the given surface of the IC chip. The IC chip can further include a vertical wire extending through the encapsulating material in a direction that is substantially perpendicular to the given surface of the IC chip and the vertical wire protruding through the other surface of the IC chip to form a vertical connector for the IC chip. The vertical connector can be coupled to the interconnect on the die.Type: ApplicationFiled: December 31, 2015Publication date: July 6, 2017Inventors: Abram M. Castro, Steven Kummerl
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Publication number: 20160268023Abstract: A transfer mold compound mixture for use in a transfer mold device to encapsulate electronic components. A ferromagnetic material is mixed into a mold compound to produce a mixed mold compound having an increased permeability over the mold compound.Type: ApplicationFiled: May 26, 2016Publication date: September 15, 2016Inventors: Steven Kummerl, Richard J. Saye
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Patent number: 9378882Abstract: Circuits and methods of fabricating circuits are disclosed herein. A method of fabricating an electronic circuit includes placing an electronic component on a substrate. A ferromagnetic material is mixed into a mold compound to produce a mixed mold compound having an increased permeability over the mold compound. The mixed mold compound is applied to the substrate by way of a transfer mold process, wherein the mixed mold compound encapsulates the electronic component.Type: GrantFiled: December 16, 2011Date of Patent: June 28, 2016Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Steven Kummerl, Richard J. Saye
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Publication number: 20160163630Abstract: A semiconductor device comprises an interposer with extruded feed-through vias and a semiconductor die. The interposers includes a substrate having a plurality of through-vias. A dielectric liner lining said through-vias. A plurality of feed-thru electrically conducting features provided by a plurality of extruded metal wires within said dielectric liner. A semiconductor die attached to said interposer.Type: ApplicationFiled: January 19, 2016Publication date: June 9, 2016Inventor: STEVEN KUMMERL
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Patent number: 9241405Abstract: A method of forming interposers includes positioning a plurality of extruded metal wires across a first platten and second platten, which secures the extruded metal wires. A sealing material is added to sidewalls of a volume having the plurality of extruded metal wires within, with the first and second plattens as end plates to form a holding volume. The holding volume is filled with a filling material. The filling material is heated to a sufficient temperature to form a heat treated filled volume. After removing the sealing material, the heat treated filled volume is sawed into a plurality of slices having a predetermined thickness to form a plurality of interposer substrates having a plurality of feed-thru conducting features provided by the plurality of extruded metal wires.Type: GrantFiled: March 6, 2013Date of Patent: January 19, 2016Assignee: TEXAS INSTRUMENTS INCORPORATEDInventor: Steven Kummerl
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Patent number: 8569082Abstract: Various exemplary embodiments provide components, devices, and methods of semiconductor packaging. The disclosed packaging component can include a mold material disposed around a lead frame and at least an integrated circuit (IC), wherein the IC is electrically connected with one side of the lead frame. The opposite side of the lead frame including, for example, lead segments, can be exposed from the mold material. A variety of other components, devices, and packages can then be assembled, e.g., over the disclosed packaging component, through the exposed regions so as to improve packaging densities.Type: GrantFiled: September 24, 2011Date of Patent: October 29, 2013Assignee: Texas Instruments IncorporatedInventors: Steven A. Kummerl, Sreenivasan K Koduri