Patents by Inventor Steven L. Hanakovic

Steven L. Hanakovic has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5620782
    Abstract: Disclosed is a parallel processor packaging structure and a method for manufacturing the structure. The individual logic and memory elements are on printed circuit cards. These printed circuit boards and cards are, in turn, mounted on or connected to circuitized flexible substrates extending outwardly from a laminate of the circuitized, flexible substrates. Intercommunication is provided through a switch structure that is implemented in the laminate. The printed circuit cards are mounted on or connected to a plurality of circuitized flexible substrates, with one printed circuit card at each end of the circuitized flexible circuit. The circuitized flexible substrates connect the separate printed circuit boards and cards through the central laminate portion. This laminate portion provides XY plane and Z-axis interconnection for inter-processor, inter-memory, inter-processor/memory element, and processor to memory bussing interconnection, and communication.
    Type: Grant
    Filed: June 2, 1995
    Date of Patent: April 15, 1997
    Assignee: International Business Machines Corporation
    Inventors: Charles R. Davis, Thomas P. Duffy, Steven L. Hanakovic, Howard L. Heck, John T. Kolias, John S. Kresge, David N. Light, Ajit K. Trivedi
  • Patent number: 5509196
    Abstract: Disclosed is a parallel processor packaging structure and a method for manufacturing the structure. The individual logic and memory elements are on printed circuit cards. These printed circuit boards and cards are, in turn, mounted on or connected to circuitized flexible substrates extending outwardly from a laminate of the circuitized, flexible substrates. Intercommunication is provided through a switch structure that is implemented in the laminate. The circuitized flexible substrates connect the separate printed circuit boards and cards through the central laminate portion. This laminate portion provides XY plane and Z-axis interconnection for inter-processor, inter-memory, inter-processor/memory element, and processor to memory bussing interconnection, and communication.
    Type: Grant
    Filed: September 21, 1994
    Date of Patent: April 23, 1996
    Assignee: International Business Machines Corporation
    Inventors: Charles R. Davis, Thomas P. Duffy, Steven L. Hanakovic, Howard L. Heck, John T. Kolias, John S. Kresge, David N. Light, Ajit K. Trivedi
  • Patent number: 5384690
    Abstract: Disclosed is a parallel processor packaging structure and a method for manufacturing the structure. The individual logic and memory elements are on printed circuit cards. These printed circuit boards and cards are, in turn, mounted on or connected to circuitized flexible substrates extending outwardly from a laminate of the circuitized, flexible substrates. Intercommunication is provided through a switch structure that is implemented in the laminate. The printed circuit cards are mounted on or connected to a plurality of circuitized flexible substrates, with one printed circuit card at each end of the circuitized flexible circuit. The circuitized flexible substrates connect the separate printed circuit boards and cards through the central laminate portion. This laminate portion provides XY plane and Z-axis interconnection for inter-processor, inter-memory, inter-processor/memory element, and processor to memory bussing interconnection, and communication.
    Type: Grant
    Filed: July 27, 1993
    Date of Patent: January 24, 1995
    Assignee: International Business Machines Corporation
    Inventors: Charles R. Davis, Thomas P. Duffy, Steven L. Hanakovic, Howard L. Heck, John T. Kolias, John S. Kresge, David N. Light, Ajit K. Trivedi
  • Patent number: 5316788
    Abstract: Process is described for applying large quantities of solder to small areas, such as the lands in a high density card, to which it is intended to surface mount electronic devices or directly attach circuitized chips. The land area is temporarily extended by depositing a relatively thin layer of metal beyond the perimeter of the land, wave soldering to deposit excess solder on the extended land region, and reflow, whereby the thin layer of metal dissolves into the solder, causing the solder to retract to the dimensions of the original land. Because the volume of solder is increased, the strength and reliability of the solder joint is greatly improved.
    Type: Grant
    Filed: July 26, 1991
    Date of Patent: May 31, 1994
    Assignee: International Business Machines Corporation
    Inventors: Eric P. Dibble, Steven L. Hanakovic, Voya R. Markovich, Daniel S. Niedrich, Gary P. Vlasak, Richard S. Zarr, Richard C. Senger