Abstract: The present invention relates to a modular, rotisserie type coating fixture for use in electronic beam physical vapor deposition (EB-PVD) coating processes. The fixture includes a support structure which rotates about a first axis during coating and a plurality of cassettes mounted within the support structure. The cassettes each hold a plurality of workpieces to be coated and are mounted in the support structure so that they rotate about axes parallel to the first axis. This allows each workpiece being coated to rotate about its longitudinal axis and to achieve an evenly distributed, substantially uniform coating on surfaces of the workpiece to be coated.

Abstract: The present invention relates to an apparatus for simultaneously coating a plurality of workpieces. The apparatus includes a modular fixture having a plurality of bushing and spindle arrangements for supporting the workpieces to be coated. The bushing and spindle arrangements allow each workpiece to rotate about its longitudinal axis. They further allow each workpiece to assume a first position where it is tilted towards a source of coating material during a first portion of the coating cycle and a second position substantially parallel to the source of coating material during a second portion of the coating cycle. By providing the novel bushing and spindle arrangement of the present invention, it is possible to coat surfaces of the workpiece which are substantially perpendicular to other surfaces of the workpiece and still obtain a substantially uniform coating along the other surfaces of the workpiece. A process for simultaneously coating the workpieces is also described.

Abstract: One or more domains are independently clocked with separate clocks. Each clock is an asynchronous stop/start clock implementing a self-tuning clocking methodology. Domain circuit speed is monitored and the clock adjusted to tune the domain to run at near maximum speed. Inter-domain data transfers are performed by a four-way handshaking method. In effect the clock period of the respective clocks during the data transfer becomes the slower period of the two domains' clock periods. An inter-domain arbiter is implemented at each domain for deciding which domain's request is to be granted during an immediate clock period. Data input to a domain is tracked to determine when data is present. When no data is present, the domain's clock is stopped.

Abstract: A field programmable gate array (FPGA) including both routing and logic blocks (RLBs) and routing and arbiter blocks (RABs) is disclosed. The RABs are periodically placed throughout the FPGA and operate either to arbitrate the arrival of simultaneous signals or to synchronize simultaneous signals. In addition, each of the RLBs are capable of operating in accordance with two clock signals and an asynchronous initialization. The combination of the RLBs and RABs allow the FPGA to operate synchronously and asynchronously.