Patents by Inventor Steven M. Eustis
Steven M. Eustis has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8239715Abstract: A method is provided for operating an interface between a first unit and a second unit supplying its data. The method includes switching control between LSSD_B and LSSD_C clocks and system clock (CLK) to provide a test mode of operation and a functional mode of operation to optimize setup and hold times depending on conditions under which the unit is operating. In the test mode, data is launched by the LSSD_C clock. In the functional mode, the data is launched by the system clock (CLK) to RAM. A method is also provided to determine which memory inputs should use a circuit that provides adequate setup and hold margins.Type: GrantFiled: June 24, 2008Date of Patent: August 7, 2012Assignee: International Business Machines CorporationInventors: Steven M. Eustis, Kevin W. Gorman, David E. Lackey, Michael R. Ouellette
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Patent number: 7937632Abstract: A design structure is embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit. The design structure includes an input register coupled to a data processing unit input and a test operation mode and functional operation mode. In the test mode operation, the register operates in a clocked mode such that, during the test operation mode, the register propagates data to the data processing unit in response to a clock signal. In the functional operation mode, the register operates in a data flush mode such that the register propagates data to the data processing unit in response to the data. The functional mode is enabled by a flush enable signal and the test mode is enabled by an opposite state of the flush enable signal.Type: GrantFiled: June 24, 2008Date of Patent: May 3, 2011Assignee: International Business Machines CorporationInventors: Steven M. Eustis, Kevin W. Gorman, David E. Lackey, Michael R. Ouellette
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Publication number: 20090319818Abstract: A method is provided for operating an interface between a first unit and a second unit supplying its data. The method includes switching control between LSSD_B and LSSD_C clocks and system clock (CLK) to provide a test mode of operation and a functional mode of operation to optimize setup and hold times depending on conditions under which the unit is operating. In the test mode, data is launched by the LSSD_C clock. In the functional mode, the data is launched by the system clock (CLK) to RAM. A method is also provided to determine which memory inputs should use a circuit that provides adequate setup and hold margins.Type: ApplicationFiled: June 24, 2008Publication date: December 24, 2009Inventors: Steven M. Eustis, Kevin W. Gorman, David E. Lackey, Michael R. Ouellette
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Publication number: 20090319841Abstract: A design structure is embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit. The design structure includes an input register coupled to a data processing unit input and a test operation mode and functional operation mode. In the test mode operation, the register operates in a clocked mode such that, during the test operation mode, the register propagates data to the data processing unit in response to a clock signal. In the functional operation mode, the register operates in a data flush mode such that the register propagates data to the data processing unit in response to the data. The functional mode is enabled by a flush enable signal and the test mode is enabled by an opposite state of the flush enable signal.Type: ApplicationFiled: June 24, 2008Publication date: December 24, 2009Inventors: Steven M. Eustis, Kevin W. Gorman, David E. Lackey, Michael R. Ouellette
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Publication number: 20080256405Abstract: A method of implementing a compilable memory structure configured for supporting multiple test methodologies includes configuring a first plurality of multiplexers for selectively coupling at least one data input path and at least one address path between an external customer connection and a corresponding internal memory connection associated therewith. A second multiplexer is configured for selectively coupling an input of a test latch between a functional memory array connection and a memory logic connection, the memory logic connection coupled to the at least one data input path, with an output of the test latch defining a data out customer connection. Flush logic is configured to direct data from the memory logic connection to the data out customer connection during a test of logic associated with a customer chip, facilitating observation of the memory logic connection at the customer chip.Type: ApplicationFiled: June 20, 2008Publication date: October 16, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Steven M. Eustis, James A. Monzel, Steven F. Oakland, Michael R. Ouellette
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Patent number: 7404125Abstract: A memory structure configured for supporting multiple test methodologies includes a first plurality of multiplexers configured for selectively coupling at least one data input path and at least one address path between an external customer connection and a corresponding internal memory connection associated therewith. A second multiplexer is configured for selectively coupling an input of a test latch between a functional memory array connection and a memory logic connection coupled to the at least one data input path, with an output of the test latch defining a data out customer connection.Type: GrantFiled: February 4, 2005Date of Patent: July 22, 2008Assignee: International Business Machines CorporationInventors: Steven M. Eustis, James A. Monzel, Steven F. Oakland, Michael R. Ouellette
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Patent number: 7210085Abstract: A method of manufacturing a device having embedded memory including a plurality of memory cells. During manufacturing test, a first test stress is applied to selected cells of the plurality of memory cells with a built-in self test. At least one weak memory cell is identified. The at least one weak memory cell is repaired. A second test stress is applied to the selected cells and the repaired cells with the built-in self test.Type: GrantFiled: December 2, 2003Date of Patent: April 24, 2007Assignee: International Business Machines CorporationInventors: Ciaran J. Brennan, Steven M. Eustis, Michael T. Fragano, Michael R. Ouellette, Neelesh G. Pai, Jeremy P. Rowland, Kevin M. Tompsett, David J. Wager
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Patent number: 6944075Abstract: A method of assigning bits to redundant regions for variable bit redundancy region boundaries in a compliable memory such as a 1-port SRAM is provided. Methods include allocating bits between the redundant regions in nearly equal proportions while minimizing the amount of chip real estate consumed by the memory. Methods also includes allocating bits in equal portions between redundant regions while occupying slightly more memory chip real estate. Methods also allocate bits into redundant regions with a simplified procedure which may or may not allocate bits into the redundant regions in equal proportions. All of the methods allow the total number of memory bits in the complied memory to be re-defined while maintaining the same allocation characteristics for each method. Accordingly, the methods allow efficient use of redundant memory bits while also conserving chip real estate or offering simplified allocation steps.Type: GrantFiled: January 5, 2005Date of Patent: September 13, 2005Assignee: International Business Machines CorporationInventors: Steven M. Eustis, Michael T. Fragano, Michael R. Ouellette
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Patent number: 6928377Abstract: Self-test architectures are provided to implement data column and row redundancy with a totally integrated self-test and repair capability in a Random Access Memory (RAM), either a Dynamic RAM (DRAM) or a Static Ram (SRAM), and are particularly applicable to compileable memories and to embedded RAM within microprocessor or logic chips. The invention uses two passes of self-test of a memory. The first pass of self-test determines the worst failing column, the column with the largest number of unique failing row addresses. After completion of the first pass of self-test, the spare column is allocated to replace the worst failing column. In the second pass of self-test, the BIST (Built In Self-Test) collects unique failing row addresses as it does today for memories with spare rows only. At the completion of the second pass of self-test, the spare rows are then allocated.Type: GrantFiled: September 9, 2003Date of Patent: August 9, 2005Assignee: International Business Machines CorporationInventors: Steven M. Eustis, Krishnendu Mondal, Michael R. Ouellette, Jeremy P. Rowland
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Patent number: 6922349Abstract: A method and structure for a read only memory (ROM) cell array has the first drain of a first transistor connected to a true bitline and a second drain of a second transistor connected to a complement bitline. The first transistor also includes a first source, and the second transistor includes a second source. The connection of the first source or the second source to ground programs the ROM cell. With the invention, only the first source or the second source is connected to the ground and the other is insulated from electrical connections. Further, the connection of the source to ground comprises an electrical connection formed during manufacturing of the first transistor and the second transistor.Type: GrantFiled: June 9, 2004Date of Patent: July 26, 2005Assignee: International Business Machines CorporationInventors: Robert L. Barry, Peter F. Croce, Steven M. Eustis, Yabin Wang
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Patent number: 6778419Abstract: A method and structure for a read only memory (ROM) cell array has the first drain of a first transistor connected to a true bitline and a second drain of a second transistor connected to a complement bitline. The first transistor also includes a first source, and the second transistor includes a second source. The connection of the first source or the second source to ground programs the ROM cell. With the invention, only the first source or the second source is connected to the ground and the other is insulated from electrical connections. Further, the connection of the source to ground comprises an electrical connection formed during manufacturing of the first transistor and the second transistor.Type: GrantFiled: March 29, 2002Date of Patent: August 17, 2004Assignee: International Business Machines CorporationInventors: Robert L. Barry, Peter F. Croce, Steven M. Eustis, Yabin Wang
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Patent number: 6721927Abstract: A method of designing an integrated circuit chip includes preparing a first macro to have a first power consumption rate, preparing a second macro to have a second power consumption rate different than the first power consumption rate, designing the circuit, measuring performance characteristics of the circuit, and substituting the second macro for the first macro to improve the performance characteristics. The first macro and the second macro have the same function, devices, surface area size, external wiring pattern, and timing characteristics.Type: GrantFiled: March 29, 2002Date of Patent: April 13, 2004Assignee: International Business Machines CorporationInventors: Peter F. Croce, Steven M. Eustis, Yabin Wang
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Publication number: 20030188266Abstract: A method of designing an integrated circuit chip includes preparing a first macro to have a first power consumption rate, preparing a second macro to have a second power consumption rate different than the first power consumption rate, designing the circuit, measuring performance characteristics of the circuit, and substituting the second macro for the first macro to improve the performance characteristics. The first macro and the second macro have the same function, devices, surface area size, external wiring pattern, and timing characteristics.Type: ApplicationFiled: March 29, 2002Publication date: October 2, 2003Applicant: International Business Machines CorporationInventors: Peter F. Croce, Steven M. Eustis, Yabin Wang
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Publication number: 20030185035Abstract: A method and structure for a read only memory (ROM) cell array has the first drain of a first transistor connected to a true bitline and a second drain of a second transistor connected to a complement bitline. The first transistor also includes a first source, and the second transistor includes a second source. The connection of the first source or the second source to ground programs the ROM cell. With the invention, only the first source or the second source is connected to the ground and the other is insulated from electrical connections. Further, the connection of the source to ground comprises an electrical connection formed during manufacturing of the first transistor and the second transistor.Type: ApplicationFiled: March 29, 2002Publication date: October 2, 2003Applicant: International Business Machines CorporationInventors: Robert L. Barry, Peter F. Croce, Steven M. Eustis, Yabin Wang
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Patent number: 6600673Abstract: A method and structure for a pair of read only memory (ROM) cells having a first latch and a second latch connected to the first latch. The first latch and the second latch behave as master and slave latches to one another. The first latch and the second latch include a write bitline connection that is permanently connected to a fixed voltage source to permanently program the first latch and the second latch to permanent ROM values.Type: GrantFiled: January 31, 2003Date of Patent: July 29, 2003Assignee: International Business Machines CorporationInventors: Peter F. Croce, Steven M. Eustis, Ronald A. Piro
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Patent number: 6570254Abstract: Mask programmable conductors of the same construction as the mask layers they define are utilized for mask vintage identification. When the actual mask layer is altered, the change is recorded within the mask itself. Mask identification can be fabricated to identify the following type of mask layers: DT—deep trench; SS—surface strap; DIFF—Diffusion; NDIFF—N Diffusion; PDIFF—P Diffusion; WL—N wells; PC—polysilicon gates; BN—N diffusion Implant; BP—P diffusion Implant; C1—first contact; M1—first metal layer; C2—second contact; and, M2—second metal layer. Conducting paths that incorporate, in series, the mask programmable conductor technology devices are: M1-C1-PC-C1-DIFF-C1-M1-C2-M2; M1-C1-PDIFF-SS-DT-SS-PDIFF-C1-M1-C2-M2; M2-C2-M1-C1-PC-C1-M1; M2-C2-M1-C1-NDIFF-WL-NDIFF-C1-M1; and, M2-C2-M1-C1-NDIFF-C1-M1-C1-PC-C1-M1. These conducting paths are electrically opened with the omission of any of the layers in the series path.Type: GrantFiled: May 31, 2001Date of Patent: May 27, 2003Assignee: International Business Machines CorporationInventors: John B. DeForge, David E. Douse, Steven M. Eustis, Erik L. Hedberg, Susan M. Litten, Endre P. Thoma
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Patent number: 6268228Abstract: Mask programmable conductors of the same construction as the mask layers they define are utilized for mask vintage identification. When the actual mask layer is altered, the change is recorded within the mask itself. Mask identification can be fabricated to identify the following type of mask layers: DT—deep trench; SS—surface strap; DIFF—Diffusion; NDIFF—N Diffusion; PDIFF—P Diffusion; WL—N wells; PC—polysilicon gates; BN—N diffusion Implant; BP—P diffusion Implant; C1—first contact; M1—first metal layer; C2—second contact; and, M2—second metal layer. Conducting paths that incorporate, in series, the mask programmable conductor technology devices are: M1-C1-PC-C1-DIFF-C1-M1-C2-M2; M1-C1-PDIFF-SS-DT-SS-PDIFF-C1-M1-C2-M2; M2-C2-M1-C1-PC-C1-M1; M2-C2-M1-C1-NDIFF-WL-NDIFF-C1-M1; and, M2-C2-M1-C1-NDIFF-C1-M1-C1-PC-C1-M1. These conducting paths are electrically opened with the omission of any of the layers in the series path.Type: GrantFiled: January 27, 1999Date of Patent: July 31, 2001Assignee: International Business Machines CorporationInventors: John B. DeForge, David E. Douse, Steven M. Eustis, Erik L. Hedberg, Susan M. Litten, Endre P. Thoma
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Patent number: 5920222Abstract: A pulse generator comprising a delay circuit uses a series of "n" delay stages to generate pulses that do not have distorted duty cycles. The output of the delay stage "n" feeds back to reset the delay stage "n-2". The output of each of the delay stages initially changes from a first logic state to a second logic stage at the leading edge of a pulse. The output of each delay stage switches back to the first logic state, or the trailing edge of the pulse, upon receipt of the feedback signal from a subsequent delay stage. The wave characteristics depend only on the rising edge of the pulse because the rising edge of the pulse of a future stage generates the falling edge of the current stage.Type: GrantFiled: April 22, 1997Date of Patent: July 6, 1999Assignee: International Business Machines CorporationInventors: Steven M. Eustis, Dale E. Pontius