Abstract: According to one aspect of the present disclosure, a method and technique for vectorization of bit-level netlists is disclosed. The method includes: receiving a bit-level netlist defining a plurality of registers; analyzing propagation of read data associated with the registers through logic of the bit-level netlist; and forming a plurality of vector-level bundles of registers based on the propagation of read data through the logic, wherein the plurality of vector-level bundles differ based on differences in references to memory arrays of the bit-level netlist by respective registers of the vector-level bundles.

Abstract: According to one aspect of the present disclosure, a method and technique for vectorization of bit-level netlists is disclosed. The method includes: receiving a bit-level netlist defining a plurality of registers; analyzing propagation of read data associated with the registers through logic of the bit-level netlist; and forming a plurality of vector-level bundles of registers based on the propagation of read data through the logic, wherein the plurality of vector-level bundles differ based on differences in references to memory arrays of the bit-level netlist by respective registers of the vector-level bundles.

Abstract: The illustrative embodiments provide a mechanism for abstraction for arrays in integrated circuit designs. The mechanism constructs abstract models directly from an analysis of the system. The abstract models are both sound and complete for safety properties: a safety property holds in the abstract model if and only if the property holds in the original model. The mechanism of the illustrative embodiments eliminates the need for iterative abstraction refinement. The mechanism of the illustrative embodiments can find small models that verify a system in some cases where other approaches are unable to find a small model. The approach constructs an abstract design from the original design. The abstracted design may have smaller arrays than the original design. The mechanism checks the correctness of the abstracted design by model checking.

Abstract: The illustrative embodiments provide a mechanism for abstraction for arrays in integrated circuit designs. The mechanism constructs abstract models directly from an analysis of the system. The abstract models are both sound and complete for safety properties: a safety property holds in the abstract model if and only if the property holds in the original model. The mechanism of the illustrative embodiments eliminates the need for iterative abstraction refinement. The mechanism of the illustrative embodiments can find small models that verify a system in some cases where other approaches are unable to find a small model. The approach constructs an abstract design from the original design. The abstracted design may have smaller arrays than the original design. The mechanism checks the correctness of the abstracted design by model checking.

Abstract: A bus protocol is disclosed for a symmetric multiprocessing computer system consisting of a plurality of nodes, each of which contains a multitude of processors, I/O devices, main memory and a system controller comprising an integrated switch with a top level cache. The nodes are interconnected by a dual concentric ring topology. The bus protocol is used to exchange snoop requests and addresses, data, coherency information and operational status between nodes in a manner that allows partial coherency results to be passed in parallel with a snoop request and address as an operation is forwarded along each ring. Each node combines it's own coherency results with the partial coherency results it received prior to forwarding the snoop request, address and updated partial coherency results to the next node on the ring. The protocol allows each node in the system to see the final coherency results without requiring the requesting node to broadcast these results to all the other nodes in the system.

Abstract: A bus protocol is disclosed for a symmetric multiprocessing computer system consisting of a plurality of nodes, each of which contains a multitude of processors, I/O devices, main memory and a system controller comprising an integrated switch with a top level cache. The nodes are interconnected by a dual concentric ring topology. The bus protocol is used to exchange snoop requests and addresses, data, coherency information and operational status between nodes in a manner that allows partial coherency results to be passed in parallel with a snoop request and address as an operation is forwarded along each ring. Each node combines it's own coherency results with the partial coherency results it received prior to forwarding the snoop request, address and updated partial coherency results to the next node on the ring. The protocol allows each node in the system to see the final coherency results without requiring the requesting node to broadcast these results to all the other nodes in the system.