Patents by Inventor Steven N. Hass

Steven N. Hass has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8088646
    Abstract: Check valve package for pb-free, single piece electronic modules, the package having an exterior and an interior, and at least one electronic device mounted within the interior of the package electrically connected to a lead-free solder ball grid array on a surface of the package, the package having a check valve between the interior and exterior of the package configured to allow flow from the interior to the exterior and to prevent flow form the exterior to the interior. The package withstands the solder reflow temperatures for the reflow of the pb-free solder balls of a ball grid array packaging of an NVSRAM during mounting on a circuit board. The package is suitable for packaging circuits containing rechargeable batteries and for packaging other electronic devices.
    Type: Grant
    Filed: January 22, 2010
    Date of Patent: January 3, 2012
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Patrick Clement Strittmatter, Joseph P. Hundt, Steven N. Hass
  • Patent number: 7675166
    Abstract: An integrated circuit package comprising an enclosure including a dielectric housing, a first electrical contact, and a second electrical contact. The dielectric housing, the first electrical contact, and the second electrical contact are configured to form a contact side of the enclosure. In addition, the first and second electrical contacts are sized to be substantially alignment insensitive for electro-mechanical connection to corresponding contacts of an end-use equipment. The enclosure encapsulates an integrated circuit die which is electrically coupled to the first and second electrical contacts. The alignment insensitive first and second electrical contacts may be electro-mechanically connected to corresponding contacts of an end-use equipment (e.g., a printer). Further, the integrated circuit package may be hosted by a peripheral device (e.g., a printer cartridge).
    Type: Grant
    Filed: May 11, 2005
    Date of Patent: March 9, 2010
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Jeff Alan Gordon, Steven N. Hass, Hal Kurkowski, Scott Jones
  • Patent number: 7675149
    Abstract: Check valve package for pb-free, single piece electronic modules, the package having an exterior and an interior, and at least one electronic device mounted within the interior of the package electrically connected to a lead-free solder ball grid array on a surface of the package, the package having a check valve between the interior and exterior of the package configured to allow flow from the interior to the exterior and to prevent flow form the exterior to the interior. The package withstands the solder reflow temperatures for the reflow of the pb-free solder balls of a ball grid array packaging of an NVSRAM during mounting on a circuit board. The package is suitable for packaging circuits containing rechargeable batteries and for packaging other electronic devices.
    Type: Grant
    Filed: September 12, 2006
    Date of Patent: March 9, 2010
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Patrick Clement Strittmatter, Joseph P. Hundt, Steven N. Hass
  • Patent number: 6330977
    Abstract: Coin-shaped one-wire communication modules with a flange for mounting convenience may be attached to contact extensions on items such as work totes for ease of communication. A host computer can keep track and locate multiple items which have mounted communication modules with use of a single data line and a single ground line for all of the modules.
    Type: Grant
    Filed: April 13, 1999
    Date of Patent: December 18, 2001
    Assignee: Dallas Semiconductor Corporation
    Inventors: Steven N. Hass, Michael L. Bolan, Nicholas M. G. Fekete, Robert D. Lee
  • Patent number: 6122704
    Abstract: Coin-shaped one-wire communication modules with a flange for mounting convenience may be attached to contact extensions on items such as work totes for ease of communication. A host computer can keep track and locate multiple items which have mounted communication modules with use of a single data line and a single ground line for all of the modules.
    Type: Grant
    Filed: March 14, 1995
    Date of Patent: September 19, 2000
    Assignee: Dallas Semiconductor Corp.
    Inventors: Steven N. Hass, Michael L. Bolan
  • Patent number: 6091318
    Abstract: A metalization layer formed as part of a bump connection/flip chip process for a semiconductor circuit is also used to form a sense resistor or other passive components. The metalization layers normal composition can also be altered so as to change or control the value of the so formed resistor or to improve the temperature stability of the resistor. Other passive components such as capacitors or inductor can also be formed in this layer.
    Type: Grant
    Filed: June 22, 1999
    Date of Patent: July 18, 2000
    Assignee: Dallas Semiconductor Corporation
    Inventors: Robert D. Lee, Gary V. Zanders, James Walling, Steven N. Hass
  • Patent number: 6036101
    Abstract: Coin-shaped one-wire communication modules with a flange for mounting convenience may be attached to contact extensions on items such as work totes for ease of communication.
    Type: Grant
    Filed: January 20, 1998
    Date of Patent: March 14, 2000
    Assignee: Dallas Semiconductor Corporation
    Inventors: Steven N. Hass, Michael L. Bolan
  • Patent number: 5998858
    Abstract: A secure electronic data module containing a monolithic semiconductor chip of the type having a memory that is protected by a combination of hardware and software mechanisms such that unauthorized access to the data stored in the memory is prevented. The monolithic semiconductor chip comprises a plurality of solder bumps for attaching the chip to a substrate that may be a printed circuit board or another chip; a multi-level interlaced power and ground lines using minimum geometries; and a detection circuit block for detecting an external trip signal that may be produced by a pre-specified change in an operating condition brought on by unauthorized accessing, or an internal trip signal that may be produced by shorting of power and ground lines or by a change in an oscillator's frequency, also associated with or appurtenant to unauthorized accessing of the secure memory.
    Type: Grant
    Filed: July 19, 1996
    Date of Patent: December 7, 1999
    Assignee: Dallas Semiconductor Corporation
    Inventors: Wendell L. Little, Stephen M. Curry, Steven N. Grider, Mark L. Thrower, Steven N. Hass, Michael L. Bolan, Ricky D. Fieseler, Bradley M. Harrington