Abstract: A method for forming thick oxide at the bottom of a trench formed in a semiconductor substrate includes forming a conformal oxide film that fills the trench and covers a top surface of the substrate. and etching the oxide film off the top surface of the substrate and inside the trench to leave a substantially flat layer of oxide having a target thickness at the bottom of the trench. The oxide film can be deposited by sub-atmospheric chemical vapor deposition processes, directional Tetraethoxysilate (TEOS) processes, or high density plasma deposition processes that form a thicker oxide at the bottom of the trench than on the sidewalls of the trench.

Abstract: A semiconductor power device includes a drift region of a first conductivity type, a well region extending above the drift region and having a second conductivity type opposite the first conductivity type, an active trench extending through the well region and into the drift region, source regions having the first conductivity type formed in the well region adjacent the active trench, and a first termination trench extending below the well region and disposed at an outer edge of an active region of the device. The sidewalls and bottom of the active trench are lined with dielectric material, and substantially filled with a first conductive layer forming an upper electrode and a second conductive layer forming a lower electrode, the upper electrode being disposed above the lower electrode and separated therefrom by inter-electrode dielectric material.

Abstract: Various embodiments for improved power devices as well as their methods of manufacture, packaging and circuitry incorporating the same for use in a wide variety of power electronic applications are disclosed. One aspect of the invention combines a number of charge balancing techniques and other techniques for reducing parasitic capacitance to arrive at different embodiments for power devices with improved voltage performance, higher switching speed, and lower on-resistance. Another aspect of the invention provides improved termination structures for low, medium and high voltage devices. Improved methods of fabrication for power devices are provided according to other aspects of the invention. Improvements to specific processing steps, such as formation of trenches, formation of dielectric layers inside trenches, formation of mesa structures and processes for reducing substrate thickness, among others, are presented.

Abstract: In accordance with an embodiment of the present invention, a semiconductor rectifier includes an insulation-filled trench formed in a semiconductor region. Strips of resistive material extend along the trench sidewalls. The strips of resistive material have a conductivity type opposite that of the semiconductor region. A conductor extends over and in contact with the semiconductor region so that the conductor and the underlying semiconductor region form a Schottky contact.

Abstract: A packaging technique that significantly reduces package resistance. According to the invention, lead frames external to the package are brought in direct contact to solder balls on the surface of the silicon die inside the package molding, eliminating resistive wire interconnections. The packaging technique of the present invention is particularly suitable for power transistors.

Abstract: A structural enhancement to a conventional DMOS process flow addresses the well-known destructive latch up problem. The additional steps include a symmetric "deep" punch-through stopper implant and additional thermal budget to remove silicon damage and distribute the ionized dopants appropriately. The purpose of the implant is to create a low resistance base region within the parasitic bipolar transistor to prevent the device from activating under high current conditions. In terms of circuit characteristics, the goal is to lower the voltage drop at node Vx in FIG. 1C during avalanche breakdown. This structure also provides a means of suppressing the phenomena of punch-through breakdown which can also lower the device's voltage reading.

Abstract: An active mask is used to etch field oxide in active areas down to an n- epitaxial substrate. After gate oxide growth, a polysilicon layer is deposited and planarized. The active mask defines the polysilicon gate critical dimension for a terrace gate DMOS structure. The edges of the polysilicon gates are self-aligned to the edges of the thick terrace gate oxide. Because no interlayer alignment is required to delineate the polysilicon gate, the design need not provide for alignment tolerance. A non-critical mask is deposited overlapping the terrace oxide. An etch back to field oxide in exposed areas is performed. An oxide-selective etch is performed to reduce the oxide thickness in source regions. Self-aligned body implantation, body contact masking and implantation, and source masking and implantation are performed. A dielectric is deposited. A source contact mask is deposited and a contact etch is performed. Source metal is deposited, and passivation layer is formed.

Abstract: A vertical power MOSFET comprising a metal base on which is disposed a highly doped n+ silicon substrate. A lightly doped epitaxial layer is grown on the substrate to form a drain region for conducting electrical charge carriers to the metal base. A gate region is disposed above the drain region and has side walls forming an aperture. Disposed on each side wall and axially aligned with the gate region are doped oxide spacers. Embedded within the source region beneath the aperture is a body region comprising a heavily doped region embedded within a lightly doped region. A source region, formed by diffusion from the doped oxide spacers, is disposed below each space and embedded within the body region.

Abstract: A process is disclosed for forming an oxide isolated semiconductor wafer which can include the formation of an associated high voltage transistor. The same wafer can include a plurality of low voltage transistors which can be connected in the form of circuitry that can control the high voltage transistor. Thus, a single IC chip can be fabricated for a power control function. The process includes bonding a first wafer to a second wafer using oxide (11/14), forming a groove (18) through the oxide (15), backfilling with epitaxially regrown semiconductor (19) to provide a high voltage section, and subsequently forming the high voltage transistor, e.g. NPN or DMOS devices, in said section.